View HY29DS163TF-13I_3163229.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

key features single power supply operation ? read, program, and erase operations from 1.8 to 2.2 v (2.0v 10%) ? ideal for battery-powered applications simultaneous read/write operations ? host system can program or erase in one bank while simultaneously reading from any sector in the other bank with zero latency between read and write operations high performance ? 120 and 130 ns access time versions with 10% power supply and 30pf load ultra low power consumption (typical values) ? automatic sleep mode current: 200 na ? standby mode current: 200 na ? read current: 5 ma (at 5 mhz) ? program/erase current: 15 ma boot-block sector architecture with 39 sectors in two banks for fast in-system code changes secured sector: an extra 64 kbyte sector that can be: ? factory locked and identifiable: 16 bytes available for a secure, random factory- programmed electronic serial number ? customer lockable: can be read, program- med, or erased just like other sectors flexible sector architecture ? sector protection allows locking of a sector or sectors to prevent program or erase operations within that sector ? temporary sector unprotect allows changes in locked sectors (requires high voltage on reset# pin) automatic erase algorithm erases any combination of sectors or the entire chip automatic program algorithm writes and verifies data at specified addresses compliant with common flash memory interface (cfi) specification minimum 100,000 write cycles per sector (1,000,000 cycles typical) compatible with jedec standards ? pinout and software compatible with single-power supply flash devices ? superior inadvertent write protection preliminary revision 1.3, april 2001 a[19:0] 20 ce# oe# reset# byte# we# 8 7 dq[7:0] dq[14:8] dq[15]/a[-1] ry/by# wp#/acc logic diagram data# polling and toggle bits ? provide software confirmation of completion of program or erase operations ready/busy# pin ? provides hardware confirmation of completion of program or erase operations erase suspend ? suspends an erase operation to allow programming data to or reading data from a sector in the same bank ? erase resume can then be invoked to complete the suspended erasure hardware reset pin (reset#) resets the device to reading array data wp#/acc input pin ? write protect (wp#) function allows hardware protection of two outermost boot sectors, regardless of sector protect status ? acceleration (acc) function provides accelerated program times fast program and erase times ? sector erase time: 1 sec typical ? byte/word program time utilizing acceleration function: 13 s typical space efficient packaging ? 48-pin tsop and 48-ball fbga packages hy29ds162/hy29ds163 16 megabit (2m x 8/1m x 16) super-low voltage, dual bank, simultaneous read/write, flash memory
2 hy29ds162/hy29ds163 r1.3/apr 01 general description the hy29ds162/hy29ds163 (hy29ds16x) is a 16 mbit, 1.8 volt-only cmos flash memory orga- nized as 2,097,152 (2m) bytes or 1,048,576 (1m) words. the device is available in 48-pin tsop and 48-ball fbga packages. word-wide data (x16) appears on dq[15:0] and byte-wide (x8) data appears on dq[7:0]. the hy29ds16x flash memory array is organized into 39 sectors in two banks. bank 1 contains eight 8 kbyte boot/parameter sectors and 3 or 7 larger sectors of 64 kbytes each, depending on the version of the device. bank 2 contains the rest of the memory array, organized as 28 or 24 sectors of 64 kbytes: the device features simultaneous read/write op- eration which allows the host system to invoke a program or erase operation in one bank and im- mediately and simultaneously read data from the other bank, except if that bank has any sectors marked for erasure, with zero latency. this re- leases the system from waiting for the completion of program or erase operations, thus improving overall system performance. the hy29ds16x can be programmed and erased in-system with a single 2.0 volt 10% v cc supply. internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage v pp power supply to perform those functions. the de- vice can also be programmed in standard eprom programmers. access times as low as 120 ns are offered for timing compatibility with the zero wait state requirements of high speed microproces- sors. to eliminate bus contention, the hy29ds16x has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is compatible with the jedec single- power-supply flash command set standard. com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. device programming is performed a byte/word at a time by executing the four-cycle program com- mand write sequence. this initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. faster programming times can be achieved by placing the hy29ds16x in the unlock bypass mode, which requires only two write cycles to program data in- stead of four. the hy29ds16x?s sector erase architecture al- lows any number of array sectors, in one or both banks, to be erased and reprogrammed without affecting the data contents of other sectors. de- vice erasure is initiated by executing the erase command sequence. this initiates an internal al- gorithm that automatically preprograms the sec- tor before executing the erase operation. as dur- ing programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. hardware sector group protection optionally disables both program and erase op- erations in any combination of the sector groups, while temporary sector group unprotect, which requires a high voltage on one pin, allows in-sys- tem erasure and code changes in previously pro- tected sector groups. erase suspend enables the user to put erase on hold in a bank for any period of time to read data from or program data to any sector in that bank that is not selected for era- sure. true background erase can thus be achieved. because the hy29ds16x features si- multaneous read/write capability, there is no need to suspend to read from a sector located within a bank that does not contain sectors marked for era- sure. the device is fully erased when shipped from the factory. addresses and data needed for the programming and erase operations are internally latched during write cycles. the host system can detect comple- tion of a program or erase operation by observing the ry/by# pin or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. after a program or erase cycle has been com- pleted, or after assertion of the reset# pin (which terminates any operation in progress), the device is ready to read data or to accept another com- 1 k n a b 2 k n a b 2 6 1 s d 9 2 y h w k 4 / b k 8 x 8 w k 2 3 / b k 4 6 x 3 w k 2 3 / b k 4 6 x 8 2 3 6 1 s d 9 2 y h w k 4 / b k 8 x 8 w k 2 3 / b k 4 6 x 7 w k 2 3 / b k 4 6 x 4 2
3 hy29ds162/hy29ds163 r1.3/apr 01 block diagram state control we# ce# reset# byte# command register a[19:0], a[-1] v cc detector timer erase voltage generator and sector switches program voltage generator address latch x-decoder y-decoder 16 mb flash memory array (2 banks, 39 sectors) 0.5 mb flash security sector y-gating data latch i/o buffers i/o control ry/by# dq[15:0] cfi control cfi data memory a[19:0], a[-1] wp#/acc oe# mand. reading data out of the device is similar to reading from other flash or eprom devices. the secured sector is an extra 64 kbyte sector capable of being permanently locked at the fac- tory or by customers. the secured indicator bit (accessed via the electronic id mode) is perma- nently set to a 1 if the part is factory locked, and permanently set to a 0 if customer lockable. this way, customer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secured sec- tor may store a secure, random 16-byte esn (elec- tronic serial number), customer code programmed at the factory, or both. customer lockable parts may utilize the secured sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. the wp#/acc pin provides access to two func- tions. the write protect function provides a hard- ware method of protecting certain boot sectors without using a high voltage. the accelerate func- tion speeds up programming operations, and is intended primarily to allow faster manufacturing throughput. two power-saving features are embodied in the hy29ds16x. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. the host can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. common flash memory interface (cfi) to make flash memories interchangeable and to encourage adoption of new flash technologies, major flash memory suppliers developed a flex- ible method of identifying flash memory sizes and configurations in which all necessary flash device parameters are stored directly on the device. parameters stored include memory size, byte/word configuration, sector configuration, necessary volt- ages and timing information. this allows one set of software drivers to identify and use a variety of different, current and future flash products. the standard which details the software interface nec- essary to access the device to identify it and to determine its characteristics is the common flash memory interface (cfi) specification. the hy29ds16x is fully compliant with this specification.
4 hy29ds162/hy29ds163 r1.3/apr 01 tsop48 a[11] a[10] 5 6 a[9] a[8] 7 8 a[19] nc 9 10 we# reset# 11 12 nc wp#/acc 13 14 ry/by# a[18] 15 16 a[17] a[7] 17 18 a[6] a[5] 19 20 a[15] a[14] 1 2 a[13] a[12] 3 4 a[4] a[3] 21 22 a[2] a[1] 23 24 dq[7] dq[14] 44 43 dq[6] dq[13] 42 41 dq[5] dq[12] 40 39 dq[4] v cc 38 37 dq[11] dq[3] 36 35 dq[10] dq[2] 34 33 dq[9] dq[1] 32 31 dq[8] dq[0] 30 29 a[16] byte# 48 47 v ss dq[15]/a[-1] 46 45 oe# v ss 28 27 ce# a[0] 26 25 pin configurations a6 b6 c6 d6 e6 f6 g6 h6 a5 b5 c5 d5 e5 f5 g5 h5 a4 b4 c4 d4 e4 f4 g4 h4 a3 b3 c3 d3 e3 f3 g3 h3 a2 b2 c2 d2 e2 f2 g2 h2 a1 b1 c1 d1 e1 f1 g1 h1 a[13] a[12] a[14] a[15] a[16] byte# dq[15]/a[-1] v ss a[9] a[8] a[10] a[11] dq[7] dq[14] dq[13] dq[6] we# reset# nc a[19] dq[5] dq[12] v cc dq[4] ry/by# wp#/acc a[18] nc dq[2] dq[10] dq[11] dq[3] a[7] a[17] a[6] a[5] dq[0] dq[8] dq[9] dq[1] a[3] a[4] a[2] a[1] a[0] ce# oe# v ss 48-ball fbga (top view, balls facing down)
5 hy29ds162/hy29ds163 r1.3/apr 01 e m a n e p y t n o i t p i r c s e d ] 0 : 9 1 [ as t u p n i . h g i h e v i t c a , s s e r d d a 6 7 5 , 8 4 0 , 1 f o e n o t c e l e s s t u p n i 0 2 e s e h t , e d o m d r o w n i e s e h t , e d o m e t y b n i . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w s d r o w ) m 1 ( 2 5 1 , 7 9 0 , 2 f o e n o t c e l e s o t ) b s l ( t u p n i ] 1 - [ a / ] 5 1 [ q d e h t h t i w d e n i b m o c e r a s t u p n i . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w s e t y b ) m 2 ( , ] 1 - [ a / ] 5 1 [ q d ] 0 : 4 1 [ q d s t u p t u o / s t u p n i e t a t s - i r t h g i h e v i t c a , s u b a t a d h t a p a t a d t i b - 6 1 a e d i v o r p s n i p e s e h t , e d o m d r o w n i . h t a p a t a d t i b - 8 n a e d i v o r p ] 0 : 7 [ q d , e d o m e t y b n i . s n o i t a r e p o e t i r w d n a d a e r r o f ] 8 : 4 1 [ q d . t u p n i s s e r d d a e t y b t i b - 1 2 e h t f o b s l e h t s a d e s u s i ] 1 - [ a / ] 5 1 [ q d d n a . e d o m e t y b n i d e t a t s - i r t n i a m e r d n a d e s u n u e r a # e t y bt u p n i . w o l e v i t c a , e d o m e t y b . e c i v e d e h t f o n o i t a r u g i f n o c d r o w / e t y b e h t s l o r t n o c . e d o m d r o w s t c e l e s h g i h , e d o m e t y b s t c e l e s w o l # e ct u p n i . w o l e v i t c a , e l b a n e p i h c r o m o r f a t a d d a e r o t d e t r e s s a e b t s u m t u p n i s i h t e h t d n a d e t a t s - i r t s i s u b a t a d e h t , h g i h n e h w . x 6 1 s d 9 2 y h e h t o t a t a d e t i r w . e d o m y b d n a t s e h t n i d e c a l p s i e c i v e d # e ot u p n i w o l e v i t c a , e l b a n e t u p t u o s n o i t a r e p o d a e r r o f d e t r e s s a e b t s u m t u p n i s i h t . d r o w a r o e t y b a r e h t e h w s e n i m r e t e d # e t y b . s n o i t a r e p o e t i r w r o f d e t a g e n d n a e r a e c i v e d e h t m o r f s t u p t u o a t a d , h g i h n e h w . n o i t a r e p o d a e r e h t g n i r u d d a e r s i . e t a t s e c n a d e p m i h g i h e h t n i d e c a l p e r a s n i p s u b a t a d e h t d n a d e l b a s i d # e wt u p n i . w o l e v i t c a , e l b a n e e t i r w o t r e d r o n i s e c n e u q e s d n a m m o c f o g n i t i r w s l o r t n o c s e k a t n o i t a r e p o e t i r w a . y a r r a y r o m e m e h t f o s r o t c e s e s a r e r o a t a d m a r g o r p # e t y b . h g i h s i # e o d n a w o l s i # e c e l i h w d e t r e s s a s i # e w n e h w e c a l p . n o i t a r e p o e t i r w e h t g n i r u d n e t t i r w s i d r o w a r o e t y b a r e h t e h w s e n i m r e t e d # t e s e rt u p n i . w o l e v i t c a , t e s e r e r a w d r a h e h t g n i t t e s e r f o d o h t e m e r a w d r a h a s e d i v o r p y l e t a i d e m m i t i , t e s e r s i e c i v e d e h t n e h w . e t a t s y a r r a d a e r e h t o t x 6 1 s d 9 2 y h e t i r w / d a e r l l a d n a d e t a t s - i r t s i s u b a t a d e h t . s s e r g o r p n i n o i t a r e p o y n a s e t a n i m r e t , d e t r e s s a s i # t e s e r e l i h w . d e t r e s s a s i t u p n i e h t e l i h w d e r o n g i e r a s d n a m m o c . e d o m y b d n a t s e h t n i e b l l i w e c i v e d e h t # y b / y r t u p t u o n i a r d n e p o . s u t a t s y s u b / y d a e r n i s i d n a m m o c e s a r e r o e t i r w a r e h t e h w s e t a c i d n i # e w l a n i f e h t f o e g d e g n i s i r e h t r e t f a d i l a v . d e t e l p m o c n e e b s a h r o s s e r g o r p y l e v i t c a s i e c i v e d e h t e l i h w w o l s n i a m e r t i . e c n e u q e s d n a m m o c a f o e s l u p . a t a d y a r r a d a e r o t y d a e r s i t i n e h w h g i h s e o g d n a , g n i s a r e r o a t a d g n i m m a r g o r p c c a / # p wt u p n i v ( e t a r e l e c c a / w o l e v i t c a , t c e t o r p e t i r w h h . ) : n o i t c n u f t c e t o r p e t i r wv t a n i p s i h t g n i c a l p l i e s a r e d n a m a r g o r p s e l b a s i d d e t c e f f a e h t . s r o t c e s t o o b d r o w k 4 / e t y b k 8 t h g i e e h t f o o w t n i s n o i t a r e p o t o o b - p o t a n i 8 3 s d n a 7 3 s r o , e c i v e d t o o b - m o t t o b a n i 1 s d n a 0 s e r a s r o t c e s v t a d e c a l p s i n i p e h t f i . e c i v e d h i s r o t c e s o w t e s o h t f o e t a t s n o i t c e t o r p e h t , e h t g n i s u d e t c e t o r p n u r o d e t c e t o r p e b o t t e s t s a l e r e w y e h t r e h t e h w o t s t r e v e r . s n o i t c e s n o i t c e t o r p n u d n a n o i t c e t o r p p u o r g r o t c e s e h t n i d e b i r c s e d d o h t e m : n o i t c n u f e t a r e l e c c av f i h h k c o l n u e h t s r e t n e e c i v e d e h t , t u p n i s i h t o t d e i l p p a s i e h t s e s u d n a , s r o t c e s d e t c e t o r p y n a s t c e t o r p n u y l i r a r o p m e t , e d o m s s a p y b . s n o i t a r e p o m a r g o r p r o f d e r i u q e r e m i t e h t e c u d e r o t n i p e h t n o e g a t l o v r e h g i h s a e c n e u q e s d n a m m o c m a r g o r p e l c y c - o w t e h t e s u n e h t d l u o w m e t s y s e h t v g n i v o m e r . e d o m s s a p y b k c o l n u e h t y b d e r i u q e r h h e h t s n r u t e r n i p e h t m o r f . n o i t a r e p o l a m r o n o t e c i v e d v t a e b t o n t s u m n i p s i h t h h , g n i m m a r g o r p d e t a r e l e c c a n a h t r e h t o s n o i t a r e p o r o f n i t l u s e r y a m d e t c e n n o c n u n i p e h t g n i v a e l . t l u s e r y a m e g a m a d e c i v e d r o . n o i t a r e p o e c i v e d t n e t s i s n o c n i v c c - - . y l p p u s r e w o p ) l a n i m o n ( t l o v - 2 v s s - - . d n u o r g l a n g i s d n a r e w o p signal descriptions
6 hy29ds162/hy29ds163 r1.3/apr 01 conventions unless otherwise noted, a positive logic (active high) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (v ih ) causes assertion of the signal. a ? # ? symbol following the signal name, e.g., reset#, indicates that the signal is asserted in the low state (v il ). see dc specifications for v ih and v il values. whenever a signal is separated into numbered bits, e.g., dq[7], dq[6], ..., dq[0], the family of bits may also be shown collectively, e.g., as dq[7:0]. the designation 0xnnnn (n = 0, 1, 2, . . . , 9, a, . . . , e, f) indicates a number expressed in hexadeci- mal notation. the designation 0bxxxx indicates a number expressed in binary notation (x = 0, 1). memory array organization the 16 mbit flash memory array is organized into 39 blocks called sectors (s0, s1, . . . , s38). a sector or several contiguous sectors are defined as a sector group . a sector is the smallest unit that can be erased and a sector group is the small- est unit that can be protected to prevent acciden- tal or unauthorized erasure. sectors are also combined into two ? super ? groups designated as banks . in the hy29ds16x, eight of the sectors, which comprise the boot block , are sized at eight kbytes (four kwords), while the remaining 31 sectors are sized at 64 kbytes (32 kwords). the boot block can be located at the bottom of the address range (hy29ds16xb) or at the top of the address range (hy29ds16xt). tables 1 and 2 define the sector addresses and corresponding array address ranges for the top and bottom boot block versions of the hy29ds16x. table 3 specifies the bank organizations and cor- responding bank addresses. see tables 7 and 8 for sector group definitions. secured sector flash memory region the secured sector (sec 2 ) feature provides a 64 kbyte (32 kword) flash memory region that en- ables permanent part identification through an electronic serial number (esn). an associated ? sec 2 indicator ? bit, which is permanently set at the factory and cannot be changed, indicates whether or not the sec 2 is locked when shipped from the factory. the device is offered with the sec 2 either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory, and has the sec 2 indicator bit perma- nently set to a ? 1 ? . the customer-lockable version is shipped with the sec 2 unprotected, allowing customers to utilize the sector in any manner they choose, and has the sec 2 indicator bit permanently set to a ? 0 ? . thus, the sec 2 indicator bit prevents customer-lockable devices from being used to re- place devices that are factory locked. the bit pre- vents cloning of a factory locked part and thus ensures the security of the esn once the product is shipped to the field. the system accesses the sec 2 through a com- mand sequence (see ? enter/exit secured sector command sequence ? ). after the system has writ- ten the enter secured sector command sequence, it may read the sec 2 by using the addresses nor- mally occupied by the boot sectors, as specified in table 4. this mode of operation continues until the system issues the exit secured sector com- mand sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to addressing the boot sectors. sec 2 programmed and protected at the factory in a factory-locked device, the sec 2 is protected when the device is shipped from the factory and cannot be modified in any way. the device is avail- able preprogrammed with one of the following: a random, secure esn only customer code both a random, secure esn and customer code in devices that have an esn, it will be located at the bottom of the lowest 8 kbyte boot sector: start- ing at byte address 0x000000 and ending at 0x00000f for a bottom boot device, and starting at byte address 0x1f0000 and ending at 0x1f000f for a top boot device.
7 hy29ds162/hy29ds163 r1.3/apr 01 table 1. hy29ds16xt (top boot block) memory array organization - t c e s r o e z i s ) w k / b k ( s s e r d d a r o t c e s 1 e d o m e t y b e g n a r s s e r d d a 2 e d o m d r o w e g n a r s s e r d d a 3 ] 9 1 [ a ] 8 1 [ a ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s2 3 / 4 6 00000xxx f f f f 0 0 x 0 - 0 0 0 0 0 0 x 0f f f 7 0 x 0 - 0 0 0 0 0 x 0 1 s2 3 / 4 6 0000 1xxx f f f f 1 0 x 0 - 0 0 0 0 1 0 x 0f f f f 0 x 0 - 0 0 0 8 0 x 0 2 s2 3 / 4 6 000 10xxx f f f f 2 0 x 0 - 0 0 0 0 2 0 x 0f f f 7 1 x 0 - 0 0 0 0 1 x 0 3 s2 3 / 4 6 000 11xxx f f f f 3 0 x 0 - 0 0 0 0 3 0 x 0f f f f 1 x 0 - 0 0 0 8 1 x 0 4 s2 3 / 4 6 0 0 10 0xxx f f f f 4 0 x 0 - 0 0 0 0 4 0 x 0f f f 7 2 x 0 - 0 0 0 0 2 x 0 5 s2 3 / 4 6 00101xxx f f f f 5 0 x 0 - 0 0 0 0 5 0 x 0f f f f 2 x 0 - 0 0 0 8 2 x 0 6 s2 3 / 4 6 0 0 1 10xxx f f f f 6 0 x 0 - 0 0 0 0 6 0 x 0f f f 7 3 x 0 - 0 0 0 0 3 x 0 7 s2 3 / 4 6 00 111xxx f f f f 7 0 x 0 - 0 0 0 0 7 0 x 0f f f f 3 x 0 - 0 0 0 8 3 x 0 8 s2 3 / 4 6 0 1000xxx f f f f 8 0 x 0 - 0 0 0 0 8 0 x 0f f f 7 4 x 0 - 0 0 0 0 4 x 0 9 s2 3 / 4 6 0 10 0 1xxx f f f f 9 0 x 0 - 0 0 0 0 9 0 x 0f f f f 4 x 0 - 0 0 0 8 4 x 0 0 1 s2 3 / 4 6 0 10 10xxx f f f f a 0 x 0 - 0 0 0 0 a 0 x 0f f f 7 5 x 0 - 0 0 0 0 5 x 0 1 1 s2 3 / 4 6 0 10 1 1xxx f f f f b 0 x 0 - 0 0 0 0 b 0 x 0f f f f 5 x 0 - 0 0 0 8 5 x 0 2 1 s2 3 / 4 6 0 1100xxx f f f f c 0 x 0 - 0 0 0 0 c 0 x 0f f f 7 6 x 0 - 0 0 0 0 6 x 0 3 1 s2 3 / 4 6 0 1 10 1xxx f f f f d 0 x 0 - 0 0 0 0 d 0 x 0f f f f 6 x 0 - 0 0 0 8 6 x 0 4 1 s2 3 / 4 6 0 1 1 10xxx f f f f e 0 x 0 - 0 0 0 0 e 0 x 0f f f 7 7 x 0 - 0 0 0 0 7 x 0 5 1 s2 3 / 4 6 0 1111xxx f f f f f 0 x 0 - 0 0 0 0 f 0 x 0f f f f 7 x 0 - 0 0 0 8 7 x 0 6 1 s2 3 / 4 6 10000xxx f f f f 0 1 x 0 - 0 0 0 0 0 1 x 0f f f 7 8 x 0 - 0 0 0 0 8 x 0 7 1 s2 3 / 4 6 1000 1xxx f f f f 1 1 x 0 - 0 0 0 0 1 1 x 0f f f f 8 x 0 - 0 0 0 8 8 x 0 8 1 s2 3 / 4 6 10 0 10xxx f f f f 2 1 x 0 - 0 0 0 0 2 1 x 0f f f 7 9 x 0 - 0 0 0 0 9 x 0 9 1 s2 3 / 4 6 100 11xxx f f f f 3 1 x 0 - 0 0 0 0 3 1 x 0f f f f 9 x 0 - 0 0 0 8 9 x 0 0 2 s2 3 / 4 6 10 10 0xxx f f f f 4 1 x 0 - 0 0 0 0 4 1 x 0f f f 7 a x 0 - 0 0 0 0 a x 0 1 2 s2 3 / 4 6 10101xxx f f f f 5 1 x 0 - 0 0 0 0 5 1 x 0f f f f a x 0 - 0 0 0 8 a x 0 2 2 s2 3 / 4 6 10 1 10xxx f f f f 6 1 x 0 - 0 0 0 0 6 1 x 0f f f 7 b x 0 - 0 0 0 0 b x 0 3 2 s2 3 / 4 6 10 111xxx f f f f 7 1 x 0 - 0 0 0 0 7 1 x 0f f f f b x 0 - 0 0 0 8 b x 0 4 2 s2 3 / 4 6 11000xxx f f f f 8 1 x 0 - 0 0 0 0 8 1 x 0f f f 7 c x 0 - 0 0 0 0 c x 0 5 2 s2 3 / 4 6 1 10 0 1xxx f f f f 9 1 x 0 - 0 0 0 0 9 1 x 0f f f f c x 0 - 0 0 0 8 c x 0 6 2 s2 3 / 4 6 1 10 10xxx f f f f a 1 x 0 - 0 0 0 0 a 1 x 0f f f 7 d x 0 - 0 0 0 0 d x 0 7 2 s2 3 / 4 6 1 10 1 1xxx f f f f b 1 x 0 - 0 0 0 0 b 1 x 0f f f f d x 0 - 0 0 0 8 d x 0 8 2 s2 3 / 4 6 11100xxx f f f f c 1 x 0 - 0 0 0 0 c 1 x 0f f f 7 e x 0 - 0 0 0 0 e x 0 9 2 s2 3 / 4 6 1110 1xxx f f f f d 1 x 0 - 0 0 0 0 d 1 x 0f f f f e x 0 - 0 0 0 8 e x 0 0 3 s2 3 / 4 6 11110xxx f f f f e 1 x 0 - 0 0 0 0 e 1 x 0f f f 7 f x 0 - 0 0 0 0 f x 0 1 3 s4 / 8 11111000 f f f 1 f 1 x 0 - 0 0 0 0 f 1 x 0f f f 8 f x 0 - 0 0 0 8 f x 0 2 3 s4 / 8 1111100 1 f f f 3 f 1 x 0 - 0 0 0 2 f 1 x 0f f f 9 f x 0 - 0 0 0 9 f x 0 3 3 s4 / 8 111110 10 f f f 5 f 1 x 0 - 0 0 0 4 f 1 x 0f f f a f x 0 - 0 0 0 a f x 0 4 3 s4 / 8 111110 11 f f f 7 f 1 x 0 - 0 0 0 6 f 1 x 0f f f b f x 0 - 0 0 0 b f x 0 5 3 s4 / 8 11111100 f f f 9 f 1 x 0 - 0 0 0 8 f 1 x 0f f f c f x 0 - 0 0 0 c f x 0 6 3 s4 / 8 1111110 1 f f f b f 1 x 0 - 0 0 0 a f 1 x 0f f f d f x 0 - 0 0 0 d f x 0 7 3 s4 / 8 11111110 f f f d f 1 x 0 - 0 0 0 c f 1 x 0f f f e f x 0 - 0 0 0 e f x 0 8 3 s4 / 8 11111111 f f f f f 1 x 0 - 0 0 0 e f 1 x 0f f f f f x 0 - 0 0 0 f f x 0 notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range in byte mode is a[19:0, -1]. the address range in word mode is a[19:0].
8 hy29ds162/hy29ds163 r1.3/apr 01 table 2. hy29ds16xb (bottom boot block) memory array organization notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range in byte mode is a[19:0, -1]. the address range in word mode is a[19:0]. - t c e s r o e z i s ) w k / b k ( s s e r d d a r o t c e s 1 e d o m e t y b e g n a r s s e r d d a 2 e d o m d r o w e g n a r s s e r d d a 3 ] 9 1 [ a ] 8 1 [ a ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s4 / 8 00000000 f f f 1 0 0 x 0 - 0 0 0 0 0 0 x 0f f f 0 0 x 0 - 0 0 0 0 0 x 0 1 s4 / 8 0000000 1 f f f 3 0 0 x 0 - 0 0 0 2 0 0 x 0f f f 1 0 x 0 - 0 0 0 1 0 x 0 2 s4 / 8 000000 10 f f f 5 0 0 x 0 - 0 0 0 4 0 0 x 0f f f 2 0 x 0 - 0 0 0 2 0 x 0 3 s4 / 8 000000 11 f f f 7 0 0 x 0 - 0 0 0 6 0 0 x 0f f f 3 0 x 0 - 0 0 0 3 0 x 0 4 s4 / 8 00000 100 f f f 9 0 0 x 0 - 0 0 0 8 0 0 x 0f f f 4 0 x 0 - 0 0 0 4 0 x 0 5 s4 / 8 00000 10 1 f f f b 0 0 x 0 - 0 0 0 a 0 0 x 0f f f 5 0 x 0 - 0 0 0 5 0 x 0 6 s4 / 8 00000 110 f f f d 0 0 x 0 - 0 0 0 c 0 0 x 0f f f 6 0 x 0 - 0 0 0 6 0 x 0 7 s4 / 8 00000 111 f f f f 0 0 x 0 - 0 0 0 e 0 0 x 0f f f 7 0 x 0 - 0 0 0 7 0 x 0 8 s2 3 / 4 6 0000 1xxx f f f f 1 0 x 0 - 0 0 0 0 1 0 x 0f f f f 0 x 0 - 0 0 0 8 0 x 0 9 s2 3 / 4 6 000 10xxx f f f f 2 0 x 0 - 0 0 0 0 2 0 x 0f f f 7 1 x 0 - 0 0 0 0 1 x 0 0 1 s2 3 / 4 6 000 11xxx f f f f 3 0 x 0 - 0 0 0 0 3 0 x 0f f f f 1 x 0 - 0 0 0 8 1 x 0 1 1 s2 3 / 4 6 0 0 10 0xxx f f f f 4 0 x 0 - 0 0 0 0 4 0 x 0f f f 7 2 x 0 - 0 0 0 0 2 x 0 2 1 s2 3 / 4 6 00101xxx f f f f 5 0 x 0 - 0 0 0 0 5 0 x 0f f f f 2 x 0 - 0 0 0 8 2 x 0 3 1 s2 3 / 4 6 0 0 1 10xxx f f f f 6 0 x 0 - 0 0 0 0 6 0 x 0f f f 7 3 x 0 - 0 0 0 0 3 x 0 4 1 s2 3 / 4 6 00 111xxx f f f f 7 0 x 0 - 0 0 0 0 7 0 x 0f f f f 3 x 0 - 0 0 0 8 3 x 0 5 1 s2 3 / 4 6 0 1000xxx f f f f 8 0 x 0 - 0 0 0 0 8 0 x 0f f f 7 4 x 0 - 0 0 0 0 4 x 0 6 1 s2 3 / 4 6 0 10 0 1xxx f f f f 9 0 x 0 - 0 0 0 0 9 0 x 0f f f f 4 x 0 - 0 0 0 8 4 x 0 7 1 s2 3 / 4 6 0 10 10xxx f f f f a 0 x 0 - 0 0 0 0 a 0 x 0f f f 7 5 x 0 - 0 0 0 0 5 x 0 8 1 s2 3 / 4 6 0 10 1 1xxx f f f f b 0 x 0 - 0 0 0 0 b 0 x 0f f f f 5 x 0 - 0 0 0 8 5 x 0 9 1 s2 3 / 4 6 0 1100xxx f f f f c 0 x 0 - 0 0 0 0 c 0 x 0f f f 7 6 x 0 - 0 0 0 0 6 x 0 0 2 s2 3 / 4 6 0 1 10 1xxx f f f f d 0 x 0 - 0 0 0 0 d 0 x 0f f f f 6 x 0 - 0 0 0 8 6 x 0 1 2 s2 3 / 4 6 0 1 1 10xxx f f f f e 0 x 0 - 0 0 0 0 e 0 x 0f f f 7 7 x 0 - 0 0 0 0 7 x 0 2 2 s2 3 / 4 6 0 1111xxx f f f f f 0 x 0 - 0 0 0 0 f 0 x 0f f f f 7 x 0 - 0 0 0 8 7 x 0 3 2 s2 3 / 4 6 10000xxx f f f f 0 1 x 0 - 0 0 0 0 0 1 x 0f f f 7 8 x 0 - 0 0 0 0 8 x 0 4 2 s2 3 / 4 6 1000 1xxx f f f f 1 1 x 0 - 0 0 0 0 1 1 x 0f f f f 8 x 0 - 0 0 0 8 8 x 0 5 2 s2 3 / 4 6 10 0 10xxx f f f f 2 1 x 0 - 0 0 0 0 2 1 x 0f f f 7 9 x 0 - 0 0 0 0 9 x 0 6 2 s2 3 / 4 6 100 11xxx f f f f 3 1 x 0 - 0 0 0 0 3 1 x 0f f f f 9 x 0 - 0 0 0 8 9 x 0 7 2 s2 3 / 4 6 10 10 0xxx f f f f 4 1 x 0 - 0 0 0 0 4 1 x 0f f f 7 a x 0 - 0 0 0 0 a x 0 8 2 s2 3 / 4 6 10101xxx f f f f 5 1 x 0 - 0 0 0 0 5 1 x 0f f f f a x 0 - 0 0 0 8 a x 0 9 2 s2 3 / 4 6 10 1 10xxx f f f f 6 1 x 0 - 0 0 0 0 6 1 x 0f f f 7 b x 0 - 0 0 0 0 b x 0 0 3 s2 3 / 4 6 10 111xxx f f f f 7 1 x 0 - 0 0 0 0 7 1 x 0f f f f b x 0 - 0 0 0 8 b x 0 1 3 s2 3 / 4 6 11000xxx f f f f 8 1 x 0 - 0 0 0 0 8 1 x 0f f f 7 c x 0 - 0 0 0 0 c x 0 2 3 s2 3 / 4 6 1 10 0 1xxx f f f f 9 1 x 0 - 0 0 0 0 9 1 x 0f f f f c x 0 - 0 0 0 8 c x 0 3 3 s2 3 / 4 6 1 10 10xxx f f f f a 1 x 0 - 0 0 0 0 a 1 x 0f f f 7 d x 0 - 0 0 0 0 d x 0 4 3 s2 3 / 4 6 1 10 1 1xxx f f f f b 1 x 0 - 0 0 0 0 b 1 x 0f f f f d x 0 - 0 0 0 8 d x 0 5 3 s2 3 / 4 6 11100xxx f f f f c 1 x 0 - 0 0 0 0 c 1 x 0f f f 7 e x 0 - 0 0 0 0 e x 0 6 3 s2 3 / 4 6 1110 1xxx f f f f d 1 x 0 - 0 0 0 0 d 1 x 0f f f f e x 0 - 0 0 0 8 e x 0 7 3 s2 3 / 4 6 11110xxx f f f f e 1 x 0 - 0 0 0 0 e 1 x 0f f f 7 f x 0 - 0 0 0 0 f x 0 8 3 s2 3 / 4 6 11111xxx f f f f f 1 x 0 - 0 0 0 0 f 1 x 0f f f f f x 0 - 0 0 0 8 f x 0
9 hy29ds162/hy29ds163 r1.3/apr 01 table 4. hy29ds16x secure sector addressing 1 k n a b 2 k n a b e c i v e d e c n e r e f e r ) t i b m ( e z i s s r o t c e s s s e r d d a k n a b ) b m ( e z i s s r o t c e s s s e r d d a k n a b t 2 6 1 s d 9 2 y h1 e l b a t2 8 3 s - 8 2 s1 1 1 = ] 7 1 : 9 1 [ a4 17 2 s - 0 s] 7 1 : 9 1 [ a 0 1 1 t 3 6 1 s d 9 2 y h1 e l b a t4 8 3 s - 4 2 s1 1 = ] 8 1 : 9 1 [ a2 13 2 s - 0 s] 8 1 : 9 1 [ a 0 1 b 2 6 1 s d 9 2 y h2 e l b a t2 0 1 s - 0 s0 0 0 = ] 7 1 : 9 1 [ a4 18 3 s - 1 1 s] 7 1 : 9 1 [ a 1 0 0 b 3 6 1 s d 9 2 y h2 e l b a t4 4 1 s - 0 s0 0 = ] 8 1 : 9 1 [ a2 18 3 s - 5 1 s] 8 1 : 9 1 [ a 1 0 sec 2 not programmed or protected at the factory if the security feature is not required, the sec 2 can be treated as an additional flash memory space of 64 kbytes. the sec 2 can be read, programmed, and erased as often as required. the sec 2 area can be protected using the following procedure: write the three-cycle enter secure sector re- gion command sequence then follow the sector protect algorithm shown in figure 1, except that reset# may be at either v ih or v id . this allows in-system protec- tion of the secure sector without raising any device pin to a high voltage. note that this method is only applicable to the secure sec- tor. once the secure sector is locked and verified, the system must write the exit secure sector command sequence to return to reading and writing the remainder of the array. sec 2 protection must be used with caution since, once protected, there is no procedure available for unprotecting the sec 2 area and none of the bits in the sec 2 memory space can be modified in any way. table 3. hy29ds16x bank options e c i v e d e z i s r o t c e s w k / b k s s e r d d a r o t c e s ] 2 1 : 9 1 [ a 1 e d o m e t y b e g n a r s s e r d d a 3 , 2 e d o m d r o w e g n a r s s e r d d a 3 , 2 t 3 6 1 / t 2 6 1 s d 9 2 y h2 3 / 4 6x x x 1 1 1 1 1f f f f f 1 x 0 - 0 0 0 0 f 1 x 0f f f f f x 0 - 0 0 0 8 f x 0 b 3 6 1 / b 2 6 1 s d 9 2 y h2 3 / 4 6x x x 0 0 0 0 0f f f f 0 0 x 0 - 0 0 0 0 0 0 x 0f f f 7 0 x 0 - 0 0 0 0 0 x 0 notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range in byte mode is a[19:0, -1]. the address range in word mode is a[19:0]. bus operations device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. the command register itself does not occupy any addressable memory location. the contents of the command register serve as inputs to an internal state ma- chine whose outputs control the operation of the device. table 5 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. certain bus operations require a high voltage on one or more device pins. those are described in table 6. read operation data is read from the hy29ds16x by using stan- dard microprocessor read cycles while placing the byte or word address on the device ? s address in- puts. the host system must drive the ce# and oe# pins low and drive we# high for a valid read operation to take place. the byte# pin deter- mines whether the device outputs array data in words (dq[15:0]) or in bytes (dq[7:0]).
10 hy29ds162/hy29ds163 r1.3/apr 01 table 5. hy29ds16x normal bus operations 1 notes: 1. l = v il , h = v ih , x = don ? t care (l or h), d out = data out, d in = data in. see dc characteristics for voltage levels. 2. address is a[19:0, -1] in byte mode and a[19:0] in word mode. 3. dq[15] is the a[-1] input in byte mode (byte# = l). 4. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the protection state of the two outermost boot sectors depends on whether they were last protected or unprotected using the method described in ? sector/sector block protection and unprotection ? . if wp#/acc = v hh , all sectors will be unprotected. n o i t a r e p o # e c # e o # e w # t e s e r c c a / # p w s s e r d d a 2 ] 0 : 7 [ q d ] 8 : 5 1 [ q d 3 h = # e t y b l = # e t y b d a e rllhhh / la n i d t u o d t u o z - h g i h e t i r wlhlh4 e t o na n i d n i d n i z - h g i h e l b a s i d t u p t u olhhhh / lx z - h g i hz - h g i hz - h g i h l a m r o n # e c y b d n a t s hxx h h x z - h g i hz - h g i hz - h g i h y b d n a t s p e e d # e cv c c v 3 . 0 xxv c c v 3 . 0 hx z - h g i hz - h g i hz - h g i h t e s e r e r a w d r a h ) y b d n a t s l a m r o n ( xxx l h / lx z - h g i hz - h g i hz - h g i h t e s e r e r a w d r a h ) y b d n a t s p e e d ( xxxv s s v 3 . 0 h / lx z - h g i hz - h g i hz - h g i h table 6. hy29ds16x bus operations requiring high voltage 1, 2 notes: 1. l = v il , h = v ih , x = don ? t care (l or h), v id = 10v nominal. see dc characteristics for voltage levels. 2. address bits not specified are don ? t care. 3. see text and appendix for additional information. 4. sa = sector address, sga = sector group address. see tables 1, 2, 7, and 8. 5. dq[15] is the a[-1] input in byte mode (byte# = l). 6. normal read, write and output disable operations are used in this mode. see table 5. 7. if wp#/acc = v il , the two outermost boot sectors remain protected. n o i t a r e p o 3 # e c # e o # e w # t e s e r ] 2 1 : 9 1 [ a ] 9 [ a ] 6 [ a ] 1 [ a ] 0 [ a ] 0 : 7 [ q d ] 8 : 5 1 [ q d # e t y b h = # e t y b l = 5 t c e t o r p p u o r g r o t c e slhlv d i a g s 4 xlhl d n i xx t c e t o r p n u r o t c e slhlv d i xxhhld n i xx r o t c e s y r a r o p m e t t c e t o r p n u 7 , 6 - -- -- -v d i - -- -- -- -- -- -- -- - e d o c r e r u t c a f u n a mllhhxv d i lll d a x 0xz - h g i h e c i v e d e d o c b 2 6 1 s d 9 2 y h llh h x v d i llh d 6 x 0 2 2 x 0z - h g i h t 2 6 1 s d 9 2 y h 9 6 x 0 b 3 6 1 s d 9 2 y h e 6 x 0 t 3 6 1 s d 9 2 y h a 6 x 0 r o t c e s t c e t o r p e t a t s d e t c e t o r p n u llh h a s 4 v d i lhl 0 0 x 0 xz - h g i h d e t c e t o r p 1 0 x 0 e r u c e s r o t c e s r o t a c i d n i t i b y r o t c a f d e k c o l llh h x v d i lhh 0 8 x 0 xz - h g i h y r o t c a f t o n d e k c o l 0 0 x 0
11 hy29ds162/hy29ds163 r1.3/apr 01 the hy29ds16x is automatically set for reading array data after device power-up and after a hard- ware reset to ensure that no spurious alteration of the memory content occurs during the power tran- sition. no command is necessary in this mode to obtain array data, and both banks of the device remain enabled for read accesses until the com- mand register contents are altered. this device features the capability of reading data from one bank of the memory while a program or erase operation is in progress in the other bank. if the host reads from an address within an eras- ing or erase-suspended sector, or from a bank where a programming operation is taking place, the device outputs status data instead of array data (see write operation status section). after com- pleting an automatic program or automatic erase algorithm within a bank, that bank automatically returns to the read array data mode. when the host issues an erase suspend com- mand, the bank specified in the command enters the erase- suspended read mode. while in that mode, the host can read data from, or program data into, any sector in that bank except the sector(s) being erased. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception noted above. the host must issue a hardware reset or the soft- ware reset command to return a sector to the read array data mode if dq[5] goes high during a pro- gram or erase cycle, or to return the device to the read array data mode while it is in the electronic id mode. write operation certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the hy29ds16x. writes to the device are performed by placing the byte or word address on the device ? s address inputs while the data to be written is input on dq[15:0] (byte# = high) or dq[7:0] (byte# = low). the host system must drive the ce# and we# pins low and drive oe# high for a valid write operation to take place. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the ? device commands ? section of this data sheet provides details on the specific device commands implemented in the hy29ds16x. accelerated program operation this device offers improved performance for pro- gramming operations through the ? accelerate (acc) ? function. this is one of two functions pro- vided by the wp#/acc pin and is intended prima- rily to allow faster manufacturing throughput at the factory. if v hh is applied to this input, the device enters the unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the host system would then use the two-cycle program command sequence as re- quired by the unlock bypass mode. removing v hh from the pin returns the device to normal op- eration. this pin must not be at v hh for operations other than accelerated programming, or device damage may result. leaving the pin floating or uncon- nected may result in inconsistent device opera- tion. write protect function the write protect function provides a hardware method of protecting certain boot sectors without using v id . this is the second function provided by the wp#/acc pin. placing this pin at v il disables program and erase operations in two of the eight 8 kbyte (4 kword) boot sectors. the affected sectors are sectors s0 and s1 in a bottom-boot device, or s37 and s38 in a top-boot device. if the pin is placed at v ih , the protection state of those two sectors reverts to whether they were last set to be protected or un- protected using the method described in the sec- tor group protection and unprotection sections. standby operation when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the oe# input. the standby mode can invoked using two methods.
12 hy29ds162/hy29ds163 r1.3/apr 01 the device enters the ce# controlled deep standby mode when the ce# and reset# pins are both held at v cc 0.3v. note that this is a more restricted voltage range than v ih . if both ce# and reset# are held at v ih , but not within v cc 0.3v, the device will be in the normal standby mode, but the standby current will be greater. the device enters the reset# controlled deep standby mode when the reset# pin is held at v ss 0.3v. if reset# is held at v il but not within v ss 0.3v, the standby current will be greater. see reset# section for additional information on the reset operation. the device requires standard access time (t ce ) for read access when the device is in any of the standby modes, before it is ready to read data. if the device is deselected during erasure or pro- gramming, it continues to draw active current until the operation is completed. sleep mode the sleep mode automatically minimizes device power consumption. this mode is automatically entered when addresses remain stable for t acc + 30 ns (typical) and is independent of the state of the ce#, we#, and oe# control signals. stan- dard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note: sleep mode is entered only when the device is in read mode. it is not entered if the device is executing an automatic algorithm, if it is in erase suspend mode, or during receipt of a command sequence. output disable operation when the oe# input is at v ih , output data from the device is disabled and the data bus pins are placed in the high impedance state. reset operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. if an operation was interrupted by the as- sertion of reset#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. current is reduced for the duration of the reset# pulse as described in the standby operation sec- tion above. if reset# is asserted during a program or erase operation, the ry/by# pin remains low (busy) until the internal reset operation is complete, which re- quires a time of t ready (during automatic algo- rithms). the system can thus monitor ry/by# to determine when the reset operation completes, and can perform a read or write operation t rb after ry/by# goes high. if reset# is asserted when a program or erase operation is not executing (ry/ by# pin is high), the reset operation is completed within a time of t rp . in this case, the host can per- form a read or write operation t rh after the re- set# pin returns high . the reset# pin may be tied to the system reset signal. thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the flash memory. sector group protect operation the hardware sector group protection feature dis- ables both program and erase operations in any combination of sector groups. a sector group con- sists of a single sector or a group of adjacent sec- tors, as specified in tables 7 and 8. this function can be implemented either in-system or by using programming equipment. it requires a high volt- age (v id ) on the reset# pin and uses standard microprocessor bus cycle timing to implement sector protection. the flow chart in figure 1 illus- trates the algorithm. the hy29ds16x is shipped with all sector groups unprotected. it is possible to determine whether a sector is protected or unprotected. see the elec- tronic id mode section for details. sector unprotect operation the hardware sector unprotection feature re-en- ables both program and erase operations in pre- viously protected sector groups. this function can be implemented either in-system or by using pro- gramming equipment. note that to unprotect any sector, all unprotected sector groups must first be protected prior to the first sector unprotect write
13 hy29ds162/hy29ds163 r1.3/apr 01 p u o r g s r o t c e s ) 1 e l b a t ( s s e r d d a p u o r g ] 2 1 : 9 1 [ a e z i s k c o l b w k / b k 0 g s0 s 00000xxx 2 3 / 4 6 1 g s3 s - 1 s 0000 1xxx 6 9 / 2 9 1 000 10xxx 000 11xxx 2 g s7 s - 4 s 0 0 1xxxxx 8 2 1 / 6 5 2 3 g s1 1 s - 8 s 0 10xxxxx 8 2 1 / 6 5 2 4 g s5 1 s - 2 1 s 0 1 1xxxxx 8 2 1 / 6 5 2 5 g s9 1 s - 6 1 s 10 0xxxxx 8 2 1 / 6 5 2 6 g s3 2 s - 0 2 s 10 1xxxxx 8 2 1 / 6 5 2 7 g s7 2 s - 4 2 s 1 10xxxxx 8 2 1 / 6 5 2 8 g s0 3 s - 8 2 s 11100xxx 6 9 / 2 9 1 1110 1xxx 11110xxx 9 g s1 3 s 11111000 4 / 8 0 1 g s2 3 s 1111100 1 4 / 8 1 1 g s3 3 s 111110 10 4 / 8 2 1 g s4 3 s 111110 11 4 / 8 3 1 g s5 3 s 11111100 4 / 8 4 1 g s6 3 s 1111110 1 4 / 8 5 1 g s7 3 s 11111110 4 / 8 6 1 g s8 3 s 11111111 4 / 8 p u o r g s r o t c e s ) 2 e l b a t ( s s e r d d a p u o r g ] 2 1 : 9 1 [ a e z i s k c o l b w k / b k 0 g s0 s 00000000 4 / 8 1 g s1 s 0000000 1 4 / 8 2 g s2 s 000000 10 4 / 8 3 g s3 s 000000 11 4 / 8 4 g s4 s 00000100 4 / 8 5 g s5 s 0000010 1 4 / 8 6 g s6 s 00000110 4 / 8 7 g s7 s 00000111 4 / 8 8 g s0 1 s - 8 s 00001xxx 6 9 / 2 9 1 000 10xxx 000 11xxx 9 g s4 1 s - 1 1 s 0 0 1xxxxx 8 2 1 / 6 5 2 0 1 g s8 1 s - 5 1 s 0 10xxxxx 8 2 1 / 6 5 2 1 1 g s2 2 s - 9 1 s 0 1 1xxxxx 8 2 1 / 6 5 2 2 1 g s6 2 s - 3 2 s 10 0xxxxx 8 2 1 / 6 5 2 3 1 g s0 3 s - 7 2 s 10 1xxxxx 8 2 1 / 6 5 2 4 1 g s4 3 s - 1 3 s 1 10xxxxx 8 2 1 / 6 5 2 5 1 g s7 3 s - 5 3 s 11100xxx 6 9 / 2 9 1 11101xxx 11110xxx 6 1 g s8 3 s 11111xxx 2 3 / 4 6 table 7. sector groups - top boot versions table 8. sector groups - bottom boot versions figure 1. sector group protect algorithm start reset# = v id wait 1 us write 0x60 to device write 0x60 to address wait 150 us write 0x40 to address read from address data = 0x01? protect another group? yes trycnt = 25? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector group protect complete trycnt = 1 set address: a[19:12] = group to protect a[6] = 0, a[1] = 1, a[0] = 0 wait 1 us
14 hy29ds162/hy29ds163 r1.3/apr 01 cycle. also, the unprotect procedure will cause all sectors to become unprotected, thus, sector groups that require protection must be protected again after the unprotect procedure is run. this procedure requires v id on the reset# pin and uses standard microprocessor bus cycle tim- ing to implement sector unprotection. the flow chart in figure 2 illustrates the algorithm. temporary sector unprotect operation this feature allows temporary unprotection of pro- tected sectors to allow changing the data in-sys- tem. temporary sector unprotect mode is acti- vated by setting the reset# pin to v id . while in this mode, formerly protected sectors can be pro- grammed or erased by invoking the appropriate commands (see device commands section). once v id is removed from reset#, all the previ- ously protected sector groups are protected again. figure 3 illustrates the algorithm. note: if wp#/acc = v il , the two outermost boot sec- tors remain protected. figure 2. sector group unprotect algorithm electronic id operation (high voltage method) the electronic id mode provides manufacturer and device identification, sector protection verification and sec 2 region protection status through identi- fier codes output on dq[7:0]. this mode is in- tended primarily for programming equipment to au- tomatically match a device to be programmed with its corresponding programming algorithm. two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], with additional requirements for obtain- ing specific data items listed in table 6. the elec- tronic id data can also be obtained by the host through specific commands issued via the com- mand register, as described later in the ? device commands ? section of this data sheet. while in the high-voltage electronic id mode, the system may read at specific addresses to obtain certain device identification and status informa- tion: a read cycle at address 0xxxx00 retrieves the manufacturer code. a read cycle at address 0xxxx01 in word mode or 0xxxx02 in byte mode returns the device code. start (note: all sector groups must be protected prior to sector unprotect) trycnt = 1 gnum = 0 reset# = v id wait 1 us write 0x60 to device write 0x60 to address set address: a[19:12] = group gnum a[6] = 1, a]1] = 1, a]0] = 0 write 0x40 to address read from address data = 0x00? gnum = 16? yes trycnt = 1000? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector group unprotect complete gnum = gnum + 1 wait 15 ms set address: a[6] = 1, a]1] = 1, a]0] = 0 wait 1 us
15 hy29ds162/hy29ds163 r1.3/apr 01 a read cycle containing a sector address (sa) in a[19:12] and the address 0x04 in a[6:0, a- 1] in byte mode, or 0x02 in a[7:0] in word mode, returns 0x01 if that sector is protected, or 0x00 if it is unprotected. a read cycle at address 0xxxx03 in word mode or 0xxxx06 in byte mode returns 0x80 if the sec 2 region is protected and locked at the fac- tory and 0x00 if it is not. start reset# = v id (all protected sectors become unprotected) perform program or erase operations reset# = v ih (all previously protected sectors return to protected state) temporary sector unprotect complete figure 3. temporary sector unprotect algorithm device commands device operations are initiated by writing desig- nated address and data command sequences into the device. addresses are latched on the falling edge of we# or ce#, whichever happens later. data is latched on the rising edge of we# or ce#, whichever happens first. a command sequence is composed of one, two or three of the following sub-segments: an unlock cycle , a command cycle and a data cycle . table 9 summarizes the composition of the valid com- mand sequences implemented in the hy29ds16x, and these sequences are fully described in table 10 and in the sections that follow. writing incorrect address and data values or writ- ing them in the improper sequence resets the hy29ds16x to the read mode. reading data the device automatically enters the read mode after device power-up, after the reset# input is asserted and upon the completion of certain com- mands. commands are not required to retrieve data in this mode. see read operation section for additional information. reset command writing the reset command resets the sectors to the read or erase-suspend mode. address bits are don ? t cares for this command. d n a m m o c e c n e u q e s s e l c y c s u b f o r e b m u n k c o l n u d n a m m o c a t a d d a e r001 e t o n t e s e r010 c e s r e t n e 2 n o i g e r210 c e s t i x e 2 n o i g e r211 m a r g o r p d r o w / e t y b211 s s a p y b k c o l n u210 s s a p y b k c o l n u t e s e r 01 1 s s a p y b k c o l n u m a r g o r p d r o w / e t y b 01 1 e s a r e p i h c411 e s a r e r o t c e s41) 2 e t o n ( 1 d n e p s u s e s a r e010 e m u s e r e s a r e010 d i c i n o r t c e l e213 e t o n y r e u q i f c014 e t o n notes: 1. any number of flash array read cycles are permitted. 2. additional data cycles may follow. see text. 3. any number of electronic id read cycles are permitted. 4. any number of cfi data read cycles are permitted. table 9. composition of command sequences
16 hy29ds162/hy29ds163 r1.3/apr 01 table 10. hy29ds16x command sequences electronic id 6 s e l c y c s u b 3 , 2 , 1 e c n e u q e s d n a m m o c e t i r w s e l c y c t s r i f d n o c e s d r i h t h t r u o f h t f i f h t x i s d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d a e r0a rd r t e s e r 7 1x x x0 f c e s r e t n e 2 n o i g e r d r o w35 5 5 a a a a 2 5 5 5 5 5 8 8 e t y b3a a a5 5 5a a a c e s t i x e 2 n o i g e r d r o w45 5 5 a a a a 2 5 5 5 5 5 0 9 x x x 0 0 e t y b4 a a a5 5 5a a a x x x m a r g o r p l a m r o n d r o w 4 5 5 5 a a a a 2 5 5 5 5 5 0 aa pd p e t y ba a a5 5 5a a a s s a p y b k c o l n u d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 0 2 e t y ba a a5 5 5a a a t e s e r s s a p y b k c o l n u2x x x0 9x x x0 0 m a r g o r p s s a p y b k c o l n u 9 2x x x0 aa pd p e s a r e p i h c d r o w 6 5 5 5 a a a a 2 5 5 5 5 5 0 8 5 5 5 a a a a 2 5 5 5 5 5 0 1 e t y ba a a5 5 5a a aa a a5 5 5a a a e s a r e r o t c e s d r o w 6 5 5 5 a a a a 2 5 5 5 5 5 0 8 5 5 5 a a a a 2 5 5a s0 3 e t y ba a a5 5 5a a aa a a5 5 5 d n e p s u s e s a r e 4 1a b0 b e m u s e r e s a r e 5 1a b0 3 e d o c r e r u t c a f u n a m d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 ) a b ( 0 90 0 x ) a b (d a e t y ba a a5 5 5a a a ) a b ( e d o c e c i v e d d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 ) a b ( 0 9 1 0 x ) a b ( b 2 6 1 ' = d 6 , t 2 6 1 ' = 9 6 b 3 6 1 ' = e 6 , t 3 6 1 ' = a 6 e t y ba a a5 5 5a a a ) a b (2 0 x ) a b ( y f i r e v t c e t o r p r o t c e s d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 ) a b ( 0 9 2 0 x ) a s ( r o t c e s d e t c e t o r p n u = 0 0 r o t c e s d e t c e t o r p = 1 0 e t y ba a a5 5 5a a a ) a b (4 0 x ) a s ( c e s 2 r o t a c i d n i n o i g e r t i b d r o w 3 5 5 5 a a a a 2 5 5 5 5 5 ) a b ( 0 9 3 0 x ) a b ( y r o t c a f t a d e k c o l d n a d e t c e t o r p t o n = 0 0 y r o t c a f t a d e k c o l d n a d e t c e t o r p = 0 8 e t y ba a a5 5 5a a a ) a b (6 0 x ) a b ( ) i f c ( e c a f r e t n i h s a l f n o m m o c y r e u q 8 d r o w 1 5 5 x ) a b ( 8 9 e t y ba a x ) a b ( see next page for legend and notes.
17 hy29ds162/hy29ds163 r1.3/apr 01 legend and notes for table 10: legend: x = don ? t care ra/rd = memory address/data for the read operation pa/pd = memory address/data for the program operation sa = a[19:12], sector address of the sector to be erased or verified (see note 3 and tables 1 and 2). ba = a[19:18] or a[19:17], depending on the device version, bank address, see note 3 and table 3. notes: 1. all values are in hexadecimal. dq[15:8] are don ? t care for unlock and command cycles. 2. all bus cycles are write operations unless otherwise noted. 3. address is a[10:0] in word mode and a[10:0, -1] in byte mode. a[19:11] are don ? t care except as follows: ? for ra and pa, a[19:11] are the upper address bits of the byte to be read or programmed. where ? sa ? is indicated, a[19:12] are the sector address. where ? ba ? is indicated, a[19:18] or a[19:17], depending on the device version, are the bank address. 4. the erase suspend command is valid only during a sector erase operation. the system may read and program in non- erasing sectors, or enter the electronic id mode, while in the erase suspend mode. 5. the erase resume command is valid only during the erase suspend mode. 6. the fourth bus cycle is a read cycle. 7. the command is required only to return to the read mode when the device is in the electronic id command mode or in the cfi query mode. it must also be issued to return to read mode if dq[5] goes high during a program or erase operation. it is not required for normal read operations. 8 this command is valid only when the device is in read mode or in electronic id mode. 9. the unlock bypass command is required prior to the unlock bypass program command. as described above, a reset command is not nor- mally required to begin reading array data. how- ever, a reset command must be issued in order to read array data in the following cases: if the device is in the electronic id mode, a reset command must be written to return to the read mode. if the device was in the erase suspend mode when the device entered the electronic id mode, writing the reset command returns the device to the erase suspend mode. note: when in the electronic id bus operation mode, the device returns to the read mode when v id is re- moved from the a[9] pin. the reset command is not required in this case. if the device is in the cfi query mode, a reset command must be written to return to the ar- ray read mode. if dq[5] (exceeded time limit) goes high dur- ing a program or erase operation, a reset com- mand must be invoked to return the sectors to the read mode (or to the erase suspend mode if the device was in erase suspend when the program command was issued). the reset command may also be used to abort certain command sequences: in a sector erase or chip erase command se- quence, the reset command may be written at any time before erasing actually begins, in- cluding, for the sector erase command, be- tween the cycles that specify the sectors to be erased (see sector erase command descrip- tion). this aborts the command and resets the device to the read mode. once erasure be- gins, however, the device ignores the reset command until the operation is complete. in a program command sequence, the reset command may be written between the se- quence cycles before programming actually be- gins. this aborts the command and resets the device to the read mode, or to the erase sus- pend mode if the program command sequence is written while the device is in the erase sus- pend mode. once programming begins, how- ever, the device ignores the reset command until the operation is complete. the reset command may be written between the cycles in an electronic id command se- quence to abort that command. as described above, once in the electronic id mode, the reset command must be written to return to the array read mode. enter /exit sec 2 command sequence the system can access the sec 2 region of the device by issuing the enter sec 2 region command sequence. the device continues to access the sec 2 region until the system issues the exit sec 2 region command sequence, which returns the device to normal operation.
18 hy29ds162/hy29ds163 r1.3/apr 01 note: a hardware reset will reset the device to the read array mode. program command the system programs the device a word or byte at a time by issuing the appropriate four-cycle pro- gram command sequence, as shown in table 10. the sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data. this ini- tiates the automatic program algorithm that auto- matically provides internally generated program pulses and verifies the programmed cell margin. the host is not required to provide further con- trols or timings during this operation. when the automatic program algorithm is complete, that bank returns to the read mode. several meth- ods are provided to allow the host to determine the status of the programming operation, as de- scribed in the write operation status section. while the automatic program algorithm is in progress in one bank, the host may read data from the non-programming bank. commands written to the device during execution of the automatic program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. to ensure data in- tegrity, the aborted program command sequence should be reinitiated once the reset operation is complete. programming is allowed in any sequence. only erase operations can convert a stored ? 0 ? to a ? 1 ? . thus, a bit cannot be programmed from a ? 0 ? back to a ? 1 ? . attempting to do so may cause that bank to halt the operation and set dq[5] to ? 1 ? , or cause the data# polling algorithm to indicate the opera- tion was successful. however, a succeeding read will show that the data is still ? 0 ? . unlock bypass/bypass program/bypass reset commands unlock bypass provides a faster method than the normal program command for the host system to program bytes or words to a bank. as shown in table 10, the unlock bypass command sequence consists of two unlock write cycles followed by a third write cycle containing the unlock bypass command, 0x20. that bank then enters the un- lock bypass mode. in this mode, a two-cycle un- lock bypass program command sequence is used instead of the standard four-cycle program se- quence to invoke a programming operation. the first cycle in this sequence contains the unlock bypass program command, 0xa0, and the sec- ond cycle specifies the program address and data, thus eliminating the initial two unlock cycles re- quired in the standard program command se- quence. additional data is programmed in the same manner. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com- mands are valid. to exit the unlock bypass mode, the host must issue the two-cycle unlock bypass reset command sequence shown in table 10. the bank specified in the first cycle of that com- mand then returns to the read array data mode. figure 4 illustrates the procedures for the normal and unlock bypass program operations. note: the device automatically enters the unlock by- pass mode when it is placed in accelerate mode via the wp#/acc pin. chip erase command the chip erase command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the chip erase command. this sequence invokes the au- tomatic erase algorithm that automatically preprograms (if necessary) and verifies the entire memory for an all zero data pattern prior to elec- trical erase. the host system is not required to provide any controls or timings during these op- erations. if all sectors in the device are protected, the de- vice returns to reading array data after approxi- mately 100 s. if at least one sector is unpro- tected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. however, even if every sector in one of the banks is protected, reads from that bank are not permitted until the completion of the automatic erase algorithm for the unprotected sectors in the other bank. commands written to the device during execution of the automatic erase algorithm are ignored. note that a hardware reset immediately terminates the chip erase operation. to ensure data integrity, the aborted chip erase command sequence should be reissued once the reset operation is complete.
19 hy29ds162/hy29ds163 r1.3/apr 01 start enable fast programming? issue unlock bypass command to bank yes no bank in unlock bypass mode? issue unlock bypass program command issue normal program command check programming status (see write operation status section) yes no last word/byte done? yes no setup next address/data for program operation yes no bank in unlock bypass mode? issue unlock bypass reset command to bank programming complete go to error recovery procedure dq[5] error exit programming verified figure 4. normal and unlock bypass programming procedures when the automatic erase algorithm is complete, the device returns to the reading array data mode. several methods are provided to allow the host to determine the status of the erase operation, as described in the write operation status section. figure 5 illustrates the chip erase procedure. sector erase command the sector erase command sequence consists of two unlock cycles, followed by a set-up com- figure 5. chip erase procedure start issue chip erase command sequence check erase status (see write operation status section) chip erase complete go to error recovery dq[5] error exit normal exit mand, two additional unlock cycles and then the sector erase command, which specifies which sector is to be erased. this sequence invokes the automatic erase algorithm that automatically preprograms (if necessary) and verifies the speci- fied sector for an all zero data pattern prior to elec- trical erase. the host system is not required to provide any controls or timings during these op- erations. after the sector erase data cycle (the sixth cycle) of the command sequence is issued, a sector erase time-out of 50 s (min) begins, measured from the rising edge of the final we# pulse in the command sequence. during this time, an addi- tional sector address and sector erase data cycle may be written into an internal sector erase buffer. this buffer may be loaded in any sequence, and the number of sectors designated for erasure may be from one sector to all sectors. the only re- striction is that the time between these additional cycles must be less than 50 s, otherwise era- sure may begin before the last address and com- mand are accepted. to ensure that all commands are accepted, it is recommended that host pro- cessor interrupts be disabled during the time that
20 hy29ds162/hy29ds163 r1.3/apr 01 start yes erase an additional sector? check erase status (see write operation status section) setup first (or next) sector address for erase operation erase complete write first five cycles of sector erase command sequence write last cycle (sa/0x30) of sector erase command sequence sector erase time-out (dq[3]) expired? no yes no go to error recovery dq[5] error exit normal exit sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence figure 6. sector erase procedure the additional sector erase commands are being issued and then be re-enabled afterwards. the system can monitor dq[3] to determine if the 50 s sector erase time-out has expired, as de- scribed in the write operation status section. if the time between additional sector erase com- mands can be assured to be less than the time- out, the system need not monitor dq[3]. any command other than sector erase or erase suspend during the time-out period resets the bank(s) to reading array data. the system must then rewrite the command sequence, including any additional sector addresses. once the sector erase operation itself has begun, only the erase suspend command is valid. all other commands are ignored. as for the chip erase command, note that a hard- ware reset immediately terminates the erase op- eration. to ensure data integrity, the aborted sec- tor erase command sequence should be reissued once the reset operation is complete. if all sectors designated for erasing are protected, the device returns to reading array data after ap- proximately 100 s. if at least one designated sector is unprotected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. if sectors in a bank are designated for erasure, read array op- erations from that bank cannot take place until the automatic erase algorithm terminates, even if all of those sectors are protected. however, the hy29ds16x ? s simultaneous read feature allows data to be read from a bank that does not contain any sectors that are designated for erasure while the erase algorithm is in progress in the other bank. when the automatic erase algorithm is complete, the device returns the erased sector(s) to the read array data mode. several methods are provided to allow the host to determine the status of the erase operation, as described in the write opera- tion status section. figure 6 illustrates the sector erase procedure. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation to program data into, or to read data from, any sector not designated for erasure. (the hy29ds16x ? s si- multaneous read feature allows data to be read from a bank that does not contain any sectors marked for erasure even while the erase opera- tion is not suspended). the command, which re-
21 hy29ds162/hy29ds163 r1.3/apr 01 quires the bank address, causes the erase opera- tion to be suspended in all sectors designated for erasure in the specified bank. this command is valid only during the sector erase operation, in- cluding during the 50 s time-out period at the end of the command sequence, and is ignored if it is issued during chip erase or programming opera- tions. the hy29ds16x requires a maximum of 20 s to suspend the erase operation if the erase suspend command is issued during active sector erasure. however, if the command is written during the sector erase time-out, the time-out is terminated and the erase operation is suspended immediately. once the erase operation has been suspended in the bank, the system can read array data from or program data into any sector in that bank that is not designated for erasure. normal read and write timings and command definitions apply. reading at any address within erase-suspended sectors produces status data on dq[7:0]. the host can use dq[7], or dq[6] and dq[2] together, to deter- mine if a sector is actively erasing or is erase-sus- pended. see ? write operation status ? for infor- mation on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspended read state and the host can initiate another pro- gramming operation (or read operation) within non- suspended sectors. the host can determine the status of a program operation during the erase- suspended state just as in the standard program- ming operation. the host may also write the electronic id com- mand sequence when the bank is in the erase suspend mode. the device allows reading elec- tronic id codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the elec- tronic id mode, the bank reverts to the erase sus- pend mode, and is ready for another valid opera- tion. see the electronic id command section for more information. the system must write the erase resume com- mand to the erase-suspended bank to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has re- sumed erasing. table 11 summarizes the erase operations in the hy29ds16x. electronic id command the electronic id mode provides manufacturer and device identification and sector protection verifi- cation through identifier codes output on dq[7:0]. this mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. notes: 1. only one simultaneous programming operation is permitted. 2. allowed only when the bank is in erase suspend state and only into a sector that is not designated for erasure. 3. output may differ if program operation is in progress. see write operation status section for additional information. 4. read from a sector that is designated for erasure while the bank is in erase suspend state. 5. read from a sector that is not designated for erasure while the bank is in erase suspend state, or read from any sector in a bank where an erase operation has not been commanded, or any read for the chip erase operation. 6. erase operation in other bank must be suspended. 7. n/a = not applicable. condition cannot exist. data = array data from addressed location. status = write operation status (see write operation status section for additional information). d n e p s u s e s a r e ? d e w o l l a g n i m m a r g o r p ? d e w o l l a 1 n o i t a r e p o d a e r m o r f t u p t u o 3 r o t c e s s e 4 r o t c e s s e - n o n 5 s s e r g o r p n i n o i t a r e p o 1 k n a b 2 k n a b 1 k n a b 2 k n a b 1 k n a b 2 k n a b 1 k n a b 2 k n a b e s a r e o na / na / ns e ys e ya / na / na t a da t a d e s a r e p i h co no no no na / na / ns u t a t ss u t a t s y l n o 1 k n a b n i e s a r e r o t c e ss e yo ns e y 2 s e y 6 s u t a t sa / na t a da t a d y l n o 2 k n a b n i e s a r e r o t c e so ns e ys e y 6 s e y 2 a / ns u t a t sa t a da t a d 2 d n a 1 s k n a b n i e s a r e r o t c e ss e ys e ys e y 2 s e y 2 s u t a t ss u t a t sa t a da t a d table 11. hy29ds16x erase operations summary 7
22 hy29ds162/hy29ds163 r1.3/apr 01 two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], as described previously in the device operations section. the electronic id data can also be obtained by the host through specific commands issued via the command register, as shown in table 10. this method does not require v id . the electronic id command sequence may be written to an address within a bank that is in the read mode or in the erase suspend mode. the command may not be written while the device is actively programming or erasing in the other bank. the electronic id command sequence is initiated by writing two unlock cycles, followed by a third write cycle that contains the bank address and the electronic id command. the addressed bank then enters the electronic id mode, and the system may read at any address in that bank any number of times, without initiating another command se- quence. a read cycle at address 0x(ba)x00, where ba is the bank address, retrieves the manufac- turer code. a read cycle at address 0x(ba)x01 in word mode or 0x(ba)x02 in byte mode returns the device code. a read cycle containing a sector address (sa) within the designated bank in a[19:12] and the address 0x04 in a[6:0, a-1] in byte mode, or 0x02 in a[7:0] in word mode, returns 0x01 if that sector is protected, or 0x00 if it is unpro- tected. a read cycle at address 0x(ba)x03 in word mode or 0x(ba)x06 in byte mode returns 0x80 if the sec 2 region is protected and locked at the factory and 0x00 if it is not. array data may be read from the other bank while the designated bank is in the electronic id mode. the system must write the reset command to exit the electronic id mode and return the bank to the normal read mode, or to the erase-suspended read mode if the bank was in that mode when the electronic id command was invoked. in the latter case, an erase resume command to that bank will continue the suspended erase operation. query command and common flash inter- face (cfi) mode the hy29ds16x is capable of operating in the common flash interface (cfi) mode. this mode allows the host system to determine the manufac- turer of the device, its operating parameters, its configuration and any special command codes that the device may accept. with this knowledge, the system can optimize its use of the chip by using appropriate timeout values, optimal voltages and commands necessary to use the chip to its full advantage. two commands are employed in association with cfi mode. the first places the device in cfi mode (query command) and the second takes it out of cfi mode (reset command). these are described in table 10. the single cycle query command is valid only when the device is in the read mode, including during erase suspend and standby states and while in electronic id command mode, but is ig- nored otherwise. the command is not valid while the hy29ds16x is in the electronic id bus opera- tion mode. the command places the bank desig- nated in the ? bank address ? field of the command in the cfi query mode. array data may be read from the other bank while the designated bank is in the cfi query mode. read cycles at appropri- ate addresses within the designated bank while in the query mode provide cfi data as described later in this section. write cycles are ignored, ex- cept for the reset command. the reset command returns the device from the cfi mode to the array read mode (even if it was in the electronic id mode when the query com- mand was issued), or to the erase suspend mode if the device was in that mode prior to entering cfi mode. the reset command is valid only when the device is in the cfi mode and as otherwise described for the normal reset command. tables 12 - 15 specify the data provided by the hy29ds16x during cfi mode. data at unspeci- fied addresses reads out as 0x00. note that a value of 0x00 for a data item normally indicates that the function is not supported. all values in these tables are in hexadecimal.
23 hy29ds162/hy29ds163 r1.3/apr 01 e d o m d r o w e d o m e t y b n o i t p i r c s e d s s e r d d a a t a d s s e r d d a a t a d " y r q " g n i r t s i i c s a e u q i n u - y r e u q 0 1 1 1 2 1 1 5 0 0 2 5 0 0 9 5 0 0 0 2 2 2 4 2 1 5 2 5 9 5 d i e c a f r e t n i l o r t n o c d n a t e s d n a m m o c r o d n e v y r a m i r p e d o c 3 1 4 1 2 0 0 0 0 0 0 0 6 2 8 2 2 0 0 0 e l b a t y r e u q d e d n e t x e m h t i r o g l a y r a m i r p r o f s s e r d d a 5 1 6 1 0 4 0 0 0 0 0 0 a 2 c 2 0 4 0 0 d i e c a f r e t n i l o r t n o c d n a t e s d n a m m o c r o d n e v e t a n r e t l a ) e n o n ( e d o c 7 1 8 1 0 0 0 0 0 0 0 0 e 2 0 3 0 0 0 0 e l b a t y r e u q d e d n e t x e m h t i r o g l a y r a d n o c e s r o f s s e r d d a ) e n o n ( 9 1 a 1 0 0 0 0 0 0 0 0 2 3 4 3 0 0 0 0 table 12. cfi mode: identification data values e d o m d r o w e d o m e t y b n o i t p i r c s e d s s e r d d a a t a d s s e r d d a a t a d v c c ) v 8 . 1 m u m i n i m , y l p p u sb 18 1 0 06 38 1 v c c ) v 2 . 2 m u m i x a m , y l p p u sc 12 2 0 08 32 2 v p p ) e n o n ( m u m i n i m , y l p p u sd 10 0 0 0a 30 0 v p p ) e n o n ( m u m i x a m , y l p p u se 10 0 0 0c 30 0 2 ( e t i r w e t y b / d r o w e l g n i s r o f t u o e m i t l a c i p y t n ) s f 14 0 0 0e 34 0 2 ( e t i r w r e f f u b e z i s m u m i x a m r o f t u o e m i t l a c i p y t n ) s 0 20 0 0 00 40 0 2 ( e s a r e k c o l b l a u d i v i d n i r o f t u o e m i t l a c i p y t n ) s m1 2a 0 0 02 4a 0 2 ( e s a r e p i h c l l u f r o f t u o e m i t l a c i p y t n ) s m2 2f 0 0 04 4f 0 2 ( e t i r w e t y b / d r o w e l g n i s r o f t u o e m i t m u m i x a m n ) p y t x3 25 0 0 06 45 0 2 ( e t i r w r e f f u b e z i s m u m i x a m r o f t u o e m i t m u m i x a m n ) p y t x4 20 0 0 08 40 0 2 ( e s a r e k c o l b l a u d i v i d n i r o f t u o e m i t m u m i x a m n ) p y t x5 24 0 0 0a 44 0 ) d e t r o p p u s t o n ( e s a r e p i h c l l u f r o f t u o e m i t m u m i x a m6 20 0 0 0c 40 0 table 13. cfi mode: system interface data values
24 hy29ds162/hy29ds163 r1.3/apr 01 e d o m d r o w e d o m e t y b n o i t p i r c s e d s s e r d d a a t a d s s e r d d a a t a d 2 ( e z i s e c i v e d n ) s e t y b7 25 1 0 0e 45 1 e d o c e c a f r e t n i e c i v e d h s a l f ) 6 1 x / 8 x s u o n o r h c n y s a = 2 0 ( 8 2 9 2 2 0 0 0 0 0 0 0 0 5 2 5 2 0 0 0 t o n ( e t i r w e t y b - i t l u m n i s e t y b f o r e b m u n m u m i x a m ) d e t r o p p u s a 2 b 2 0 0 0 0 0 0 0 0 4 5 6 5 0 0 0 0 s n o i g e r k c o l b e s a r e f o r e b m u nc 22 0 0 08 52 0 n o i t a m r o f n i 1 n o i g e r k c o l b e s a r e 1 - n o i g e r n i s k c o l b f o # = ] d 2 , e 2 [ s e t y b - 6 5 2 f o s e l p i t l u m n i e z i s = ] f 2 , 0 3 [ d 2 e 2 f 2 0 3 7 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 a 5 c 5 e 5 0 6 7 0 0 0 0 2 0 0 n o i t a m r o f n i 2 n o i g e r k c o l b e s a r e 1 3 2 3 3 3 4 3 e 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 6 4 6 6 6 8 6 e 1 0 0 0 0 1 0 table 14. cfi mode: device geometry data values e d o m d r o w e d o m e t y b n o i t p i r c s e d s s e r d d a a t a d s s e r d d a a t a d " i r p " g n i r t s i i c s a e u q i n u - y r e u q 0 4 1 4 2 4 0 5 0 0 2 5 0 0 9 4 0 0 0 8 2 8 4 8 0 5 2 5 9 4 i i c s a , r e b m u n n o i s r e v r o j a m3 41 3 0 06 81 3 i i c s a , r e b m u n n o i s r e v r o n i m4 40 3 0 08 80 3 k c o l n u e v i t i s n e s s s e r d d a ) d e r i u q e r t o n = 1 , d e r i u q e r = 0 ( 5 40 0 0 0a 80 0 d n e p s u s e s a r e e t i r w d n a d a e r o t = 2 ( )6 42 0 0 0c 82 0 t c e t o r p r o t c e s ) p u o r g / s r o t c e s f o # = n ( 7 41 0 0 0e 81 0 t c e t o r p n u r o t c e s y r a r o p m e t ) d e t r o p p u s = 1 ( 8 41 0 0 00 91 0 e m e h c s t c e t o r p n u / t c e t o r p r o t c e s ) d o h t e m a 0 0 8 v l 9 2 m a = 4 ( 9 44 0 0 02 94 0 n o i t a r e p o w / r s u o e n a t l u m i s ) 8 1 = 3 6 1 s d 9 2 y h , c 1 = 2 6 1 s d 9 2 y h : 2 k n a b n i s r o t c e s f o r e b m u n = x x ( a 4 r o c 1 0 0 8 1 0 0 4 9 r o c 1 8 1 e p y t e d o m t s r u b ) d e t r o p p u s t o n = 0 ( b 40 0 0 06 90 0 e p y t e d o m e g a p ) d e t r o p p u s t o n = 0 ( c 40 0 0 08 90 0 ) v 5 . 8 ( m u m i n i m y l p p u s c c ad 45 8 0 0a 95 8 ) v 5 . 9 ( m u m i x a m y l p p u s c c ae 45 9 0 0c 95 9 n o i s r e v t o o b m o t t o b / p o t ) t o o b p o t = b t , t o o b m o t t o b = b b ( f 4 ) b b ( 2 0 0 0 ) b t ( 3 0 0 0 e 9 ) b b ( 2 0 ) b t ( 3 0 table 15. cfi mode: vendor-specific extended query data values
25 hy29ds162/hy29ds163 r1.3/apr 01 write operation status the hy29ds16x provides a number of facilities to determine the status of a program or erase op- eration. these are the ry/by# (ready/busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. table 16 summarizes the sta- tus indications and further detail is provided in the subsections which follow. ry/by# - ready/busy# ry/by# is an open-drain output pin that indicates whether a programming or erase automatic algo- rithm is in progress or has completed. a pull-up resistor to v cc is required for proper operation. ry/ by# is valid after the rising edge of the final we# pulse in the corresponding command sequence, including during the sector erase time-out. if the output is low (busy), the device is actively erasing or programming, including programming while in the erase suspend mode. if the output is high (ready), the device has completed the op- eration and is ready to read array data, is in the standby mode, or at least one bank is in the erase- suspend read mode. table 16. write and erase operation status summary notes: 1. a valid address within the bank where an automatic algorithm is in progress is required when reading status information except ry/by#. for a programming operation, the address used for the read cycle should be the program address. for an erase operation, the address used for the read cycle should be any address within a non-protected sector marked for erasure (any address for the chip erase operation). 2. dq[5] status switches to a ? 1 ? when a program or erase operation exceeds the maximum timing limit. 3. a ? 1 ? during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. dq[3] is not applicable to the chip erase operation. 4. equivalent to ? no toggle ? because data is obtained in this state. for ? erase completed ? , 5. data (dq[7:0]) = 0xff immediately after erasure. 6. programming can be done only in a non-suspended sector (a sector not specified for erasure). e d o m n o i t a r e p o ] 7 [ q d 1 ] 6 [ q d ] 5 [ q d ] 3 [ q d ] 2 [ q d 1 # y b / y r l a m r o n s s e r g o r p n i g n i m m a r g o r p# ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r pa t a da t a d 4 a t a da t a da t a d1 s s e r g o r p n i e s a r e0e l g g o t1 / 0 2 1 3 e l g g o t0 d e t e l p m o c e s a r e 5 a t a da t a d 4 a t a da t a da t a d 4 1 e s a r e d n e p s u s d e d n e p s u s e s a r e n i h t i w d a e r r o t c e s 1e l g g o t o n0a / ne l g g o t1 e s a r e - n o n n i h t i w d a e r r o t c e s d e d n e p s u s a t a da t a da t a da t a da t a d1 s s e r g o r p n i g n i m m a r g o r p 6 # ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r p 6 a t a da t a d 4 a t a da t a da t a d1 dq[7] - data# polling the data# polling bit, dq[7], indicates to the host system whether an automatic algorithm is in progress or completed, or whether a bank is in erase suspend mode. data# polling is valid after the rising edge of the final we# pulse in the pro- gram or erase command sequence. while a programming operation is in progress, the device outputs the complement of the value pro- grammed to dq[7]. when the programming op- eration is complete, the device outputs the value programmed to dq[7]. if a program operation is attempted within a protected sector, data# poll- ing on dq[7] is active for approximately 1 s, then the device returns to reading array data. the host system must do a read at the program address to obtain valid programming status information on this bit. during an erase operation, data# polling produces a ? 0 ? on dq[7]. when the erase operation is com- plete, or if the bank enters the erase suspend mode, data# polling produces a ? 1 ? on dq[7]. the host must read at an address within any of the non-protected sectors designated for erasure to
26 hy29ds162/hy29ds163 r1.3/apr 01 obtain valid erase status information on dq[7]. if all sectors designated for erasing are protected, data# polling on dq[7] is active for approximately 100 s, then the bank returns to reading array data. when the system detects that dq[7] has changed from the complement to true data (or ? 0 ? to ? 1 ? for erase), it should do an additional read cycle to ensure that valid data is read on dq[7:0] or dq[15:0]. this is because dq[7] may change asynchronously with respect to the other data bits while output enable (oe#) is asserted low. figure 7 shows the data# polling test algorithm. dq[6] - toggle bit i toggle bit i on dq[6] indicates whether an auto- matic program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address within the programming or erasing bank and is valid after the rising edge of the final we# pulse in the program or erase com- mand sequence, including during the sector erase time-out. the system may use either oe# or ce# to control the read cycles. during an automatic program algorithm operation (including programming while in erase suspend mode), successive read cycles at any address in the bank where the program operation is taking place cause dq[6] to toggle. dq[6] stops tog- gling when the operation is complete. if a pro- gram address falls within a protected sector, dq[6] toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. while erasing, successive read cycles within any sector designated for erasure (or any sector for the chip erase operation) cause dq[6] to toggle. dq[6] stops toggling when the erase operation is complete or when the device is placed in the erase suspend mode. the host may use dq[2] to de- termine which sectors are erasing or erase-sus- pended (see below). after an erase command sequence is written, if all the sectors designated for erasure are pro- tected, dq[6] toggles for approximately 100 s, and the device then returns to reading array data. dq[2] - toggle bit ii toggle bit ii, dq[2], when used with dq[6], indi- cates whether a particular sector is actively eras- ing or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. the device toggles dq[2] with each oe# or ce# read cycle. dq[2] toggles when the host reads at addresses within sectors that have been designated for era- sure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. dq[6], by comparison, indicates whether the device is actively erasing, or is in erase suspend, but can- not distinguish which sectors are designated for erasure. thus, both status bits are required for sector and mode information. figure 8 illustrates the operation of toggle bits i and ii. start read dq[7:0] at valid address (note 1) dq[7] = data? no yes program/erase complete dq[5] = 1? no yes test for dq[7] = 1? for erase operation read dq[7:0] at valid address (note 1) dq[7] = data? (note 2) no yes test for dq[7] = 1? for erase operation program/erase exceeded time error notes: 1. during programming , the program address. during sector erase , an address within any non-protected sector specified for erasure. during chip erase , an address within any non-protected sector. 2. recheck dq[7] since it may change asynchronously to dq[5]. figure 7. data# polling test algorithm
27 hy29ds162/hy29ds163 r1.3/apr 01 dq[5] - exceeded timing limits dq[5] is set to a ? 1 ? when the program or erase time has exceeded a specified internal pulse count limit. this is a failure condition that indicates that the program or erase cycle was not successfully completed. dq[5] status is valid only while dq[7] or dq[6] indicate that the automatic algorithm is in progress. the dq[5] failure condition will also be signaled if the host tries to program a ? 1 ? to a location that is previously programmed to ? 0 ? , since only an erase operation can change a ? 0 ? to a ? 1 ? . for both of these conditions, the host must issue a reset command to return the device to the read mode. dq[3] - sector erase timer after writing a sector erase command sequence, the host may read dq[3] to determine whether or not an erase operation has begun. when the read dq[7:0] at valid address (note 1) dq[6] toggled? no (note 3) yes program/erase complete dq[5] = 1? no yes read dq[7:0] at valid address (note 1) dq[6] toggled? (note 2) no yes program/erase exceeded time error notes : 1. during programming, the program address. during sector erase, an address within any sector scheduled for erasure. 2. recheck dq[6] since toggling may stop at the same time as dq[5] changes from 0 to 1. 3. use this path if testing for program/erase status. 4. use this path to test whether sector is in erase suspend mode. read dq[7:0] at valid address (note 1) start read dq[7:0] dq[2] toggled? no sector being read is in erase suspend read dq[7:0] yes no (note 4) sector being read is not in erase suspend figure 8. toggle bit i and ii test algorithm sector erase time-out expires and the sector erase operation commences, dq[3] switches from a ? 0 ? to a ? 1 ? . refer to the ? sector erase command ? section for additional information. note that the sector erase timer does not apply to the chip erase command. after the initial sector erase command sequence is issued, the system should read the status on dq[7] (data# polling) or dq[6] (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq[3]. if dq[3] is a ? 1 ? , the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than erase suspend) are ignored until the erase operation is complete. if dq[3] is a ? 0 ? , the device will accept a sector erase data cycle to mark an additional sector for erasure. to ensure that the data cycles have been accepted, the system software should check the status of dq[3] prior to and following each subsequent sector erase data cycle. if dq[3] is high on the second status check, the last data cycle might not have been accepted.
28 hy29ds162/hy29ds163 r1.3/apr 01 hardware data protection the hy29ds16x provides several methods of pro- tection to prevent accidental erasure or program- ming which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. these methods are described in the sections that follow. command sequences commands that may alter array data require a sequence of cycles as described in table 10. this provides data protection against inadvertent writes. low v cc write inhibit to protect data during v cc power-up and power- down, the device does not accept write cycles when v cc is less than v lko (typically 1.4 volts). the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by asserting any one of the following conditions: oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power- up. sector protection additional data protection is provided by the hy29ds16x ? s sector protect features, described previously, which can be used to protect sensitive areas of the flash array from accidental or unau- thorized attempts to alter the data.
29 hy29ds162/hy29ds163 r1.3/apr 01 absolute maximum ratings 1 l o b m y s r e t e m a r a p e u l a v t i n u t g t s e r u t a r e p m e t e g a r o t s 0 5 1 + o t 5 6 -c o t s a i b d e i l p p a r e w o p h t i w e r u t a r e p m e t t n e i b m a 5 2 1 + o t 5 5 -c o v 2 n i v o t t c e p s e r h t i w n i p n o e g a t l o v s s : v c c 2 c c a / # p w 3 # t e s e r , # e o , ] 9 [ a 3 s n i p r e h t o l l a 2 5 . 2 + o t 5 . 0 - 5 . 0 1 + o t 5 . 0 - 0 . 1 1 + o t 5 . 0 - v ( o t 5 . 0 - c c ) 5 . 0 + v v v v i s o t n e r r u c t i u c r i c t r o h s t u p t u o 4 0 0 1a m notes: 1. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 2. minimum dc voltage on input or i/o pins is ? 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 9. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 10. 3. minimum dc input voltage on pins wp#/acc, a[9], oe#, and reset# is -0.5 v. during voltage transitions, a[9], oe# and reset# may undershoot v ss to -2.0 v for periods of up to 20 ns. see figure 9. maximum dc input voltage on pins a[9], oe#, and reset#] is +11.0 v which may overshoot to 12.5 v for periods up to 20 ns. maximum dc input voltage on pin wp#/acc is +10.5 v which may overshoot to 12.0 v for periods up to 20 ns. 4. no more than one output at a time may be shorted to v ss . duration of the short circuit should be less than one second. recommended operating conditions 1 l o b m y s r e t e m a r a p e u l a v t i n u t a : e r u t a r e p m e t g n i t a r e p o t n e i b m a s e c i v e d e r u t a r e p m e t l a i c r e m m o c s e c i v e d e r u t a r e p m e t l a i r t s u d n i 0 7 + o t 0 5 8 + o t 0 4 - c o c o v c c e g a t l o v y l p p u s g n i t a r e p o 2 . 2 + o t 8 . 1 +v notes: 1. recommended operating conditions define those limits between which the functionality of the device is guaranteed. 2.0 v v cc + 0.5 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 9. maximum undershoot waveform figure 10. maximum overshoot waveform 0.8 v - 0.5 v - 2.0 v 20 ns 20 ns 20 ns
30 hy29ds162/hy29ds163 r1.3/apr 01 dc characteristics r e t e m a r a p n o i t p i r c s e d p u t e s t s e t 2 n i m p y t x a m t i n u i i l t n e r r u c d a o l t u p n iv n i v = s s v o t c c 0 . 1 a i t i l t n e r r u c d a o l t u p n i ] 9 [ av 0 . 1 1 = ] 9 [ a5 3a i o l t n e r r u c e g a k a e l t u p t u ov t u o v = s s v o t c c 0 . 1 a i 1 c c v c c t n e r r u c d a e r e v i t c a 1 v = # e c l i , v = # e o h i , e d o m e t y b z h m 550 1a m z h m 112a m v = # e c l i , v = # e o h i , e d o m d r o w z h m 550 1a m z h m 112a m i 2 c c v c c e t i r w e l i h w d a e r e v i t c a t n e r r u c ) e s a r e r o m a r g o r p ( 1 v = # e c l i , v = # e o h i , e d o m e t y b z h m 59 14 2a m z h m 16 11 2a m v = # e c l i , v = # e o h i , e d o m d r o w z h m 59 14 2a m z h m 16 11 2a m i 3 c c v c c t n e r r u c e t i r w e v i t c a 4 , 3 v = # e c l i ,v = # e o h i 5 10 2a m i 4 c c v c c p e e d d e l l o r t n o c # e c t n e r r u c y b d n a t s v = # e c c c , v 3 . 0 v = # t e s e r c c v 3 . 0 2 . 05a i 5 c c v c c p e e d d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s v = # t e s e r s s v 3 . 0 2 . 05a i 6 c c e d o m p e e l s c i t a m o t u a t n e r r u c 5 v h i v = c c , v 3 . 0 v l i v = s s v 3 . 0 2 . 05a i 7 c c v c c l a m r o n d e l l o r t n o c # e c t n e r r u c y b d n a t s v = # t e s e r = # e c h i 0 60 0 3a i 8 c c v c c d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s l a m r o n 2 v = # t e s e r l i 0 60 0 3a i c c a , t n e r r u c m a r g o r p d e t a r e l e c c a e d o m d r o w r o e t y b v = # e c l i , v = # e o h i v h h 50 1a m v c c 0 15 1a m v l i e g a t l o v w o l t u p n i5 . 0 -v x 2 . 0 c c v v h i e g a t l o v h g i h t u p n ix 8 . 0v c c v c c 3 . 0 +v v d i d n a d i c i n o r t c e l e r o f e g a t l o v t c e t o r p n u r o t c e s y r a r o p m e t v c c v 0 . 2 =0 . 90 . 1 1v v h h m a r g o r p r o f e g a t l o v n o i t a r e l e c c a v c c v 0 . 2 =5 . 85 . 9v v 1 l o e g a t l o v w o l t u p t u o v c c v = c c , n i m i l o a m 0 . 2 = 5 2 . 0v v 2 l o v c c v = c c , n i m i l o 0 0 1 =a 1 . 0v v 1 h o e g a t l o v h g i h t u p t u o v c c v = c c , n i m i h o a m 0 . 2 - = x 7 . 0v c c v v 2 h o v c c v = c c , n i m i h o 0 0 1 - =a v c c 1 . 0 -v v o k l v w o l c c e g a t l o v t u o k c o l 4 2 . 15 . 1v notes: 1. the i cc current is listed is typically less than 1 ma/mhz with oe# at v ih . typical v cc is 2.0 v. 2. all parameters are tested with v cc = v cc max unless otherwise noted. 3. i cc active while the automatic erase or automatic program algorithm is in progress. 4. not 100% tested. 5. automatic sleep mode is enabled when addresses remain stable for t acc + 30 ns (typical).
31 hy29ds162/hy29ds163 r1.3/apr 01 dc characteristics zero power flash figure 11. i cc1 current vs. time (showing active and automatic sleep currents) note: addresses are switching at 1 mhz. figure 12. typical i cc1 current vs. frequency note: t = 25 c. 0 500 1000 1500 2000 2500 3000 3500 4000 0 5 10 15 20 time in ns supply current in ma 123456 0 2 4 6 10 frequency in mhz supply current in ma 8 1.8 v 2.2 v
32 hy29ds162/hy29ds163 r1.3/apr 01 test conditions table 17. test specifications figure 13. test setup figure 14. input waveforms and measurement levels t s e t n o i t i d n o c d e e p s l l a s n o i s r e v t i n u d a o l t u p t u o3 1 e r u g i f c ( e c n a t i c a p a c d a o l t u p t u o l )0 3f p s e m i t l l a f d n a e s i r t u p n i5s n l e v e l w o l l a n g i s t u p n i0 . 0v l e v e l h g i h l a n g i s t u p n i0 . 2v t n e m e r u s a e m g n i m i t t u p n i l e v e l l a n g i s 0 . 1v t n e m e r u s a e m g n i m i t t u p t u o l e v e l l a n g i s 0 . 1v m r o f e v a w s t u p n i s t u p t u o y d a e t s l o t h m o r f g n i g n a h c h o t l m o r f g n i g n a h c d e t t i m r e p e g n a h c y n a , e r a c t ' n o dn w o n k n u e t a t s , g n i g n a h c y l p p a t o n s e o d e t a t s e c n a d e p m i h g i h s i e n i l r e t n e c ) z h g i h ( key to switching waveforms 16.7 kohm c l 16.7 kohm v cc device under test out measurement level 1.0 v output input 1.0 v 0.0 v 2.0 v note: timing measurements are made at the reference levels specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurement is made
33 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics read operations notes: 1. not 100% tested. addresses stable t rc t acc output valid t oe t ce t oeh t oh t df ry/by# 0 v reset# outputs we# oe# ce# addresses figure 15. read operation timings r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t v a v a t c r e m i t e l c y c d a e r 1 n i m0 2 10 3 1s n t v q v a t c c a y a l e d t u p t u o o t s s e r d d a v = # e c l i v = # e o l i x a m0 2 10 3 1s n t v q l e t e c y a l e d t u p t u o o t e l b a n e p i h cv = # e o l i x a m0 2 10 3 1s n t z q h e t f d z h g i h t u p t u o o t e l b a n e p i h c 1 x a m0 50 5s n t v q l g t e o y a l e d t u p t u o o t e l b a n e t u p t u ov = # e c l i x a m0 50 5s n t z q h g t f d z h g i h t u p t u o o t e l b a n e t u p t u o 1 x a m0 50 5s n t h e o e l b a n e t u p t u o e m i t d l o h 1 d a e rn i m0s n d n a e l g g o t g n i l l o p # a t a d n i m0 2s n t x q x a t h o # e c , s e s s e r d d a m o r f e m i t d l o h t u p t u o t s r i f s r u c c o r e v e h c i h w , # e o r o 1 n i m0s n
34 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics hardware reset (reset#) notes: 1. not 100% tested. figure 16. reset# timings reset timings not during automatic algorithms reset timings during automatic algorithms ry/by# 0 v t rp t ready ce#, oe# reset# t rh ry/by# t rp t ready ce#, oe# reset# t rb r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t y d a e r c i t a m o t u a g n i r u d ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a 1 x a m0 2s t y d a e r g n i r u d t o n ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a c i t a m o t u a 1 x a m0 0 5s n t p r h t d i w e s l u p # t e s e rn i m0 0 5s n t h r d a e r e r o f e b e m i t h g i h # t e s e r 1 n i m0 0 1s n t d p r e d o m y b d n a t s o t w o l # t e s e rx a m0 2s t b r e m i t y r e v o c e r # y b / y rn i m0s n
35 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics word/byte configuration (byte#) r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t l f l e w o l g n i h c t i w s # e t y b o t # e cx a m0 1s n t h f l e h g i h g n i h c t i w s # e t y b o t # e cx a m0 1s n t z q l f z - h g i h t u p t u o o t w o l g n i h c t i w s # e t y bx a m0 60 6s n t v q h f e v i t c a t u p t u o o t h g i h g n i h c t i w s # e t y bn i m0 2 10 3 1s n data output dq[14:0] data output dq[7:0] data output dq[7:0] data output dq[14:0] output dq[15] address input a-1 address input a-1 data output dq[15] t elfl t elfh t fhqv t flqz ce# oe# byte# dq[14:0] dq[15]/a-1 byte# dq[14:0] dq[15]/a-1 byte# switching from word to byte mode byte# switching from byte to word mode figure 17. byte# timings for read operations figure 18. byte# timings for write operations t set (t as ) t hold (t ah ) falling edge of the last we# signal ce# we# byte# note: refer to the program/erase operations table for t as and t ah specifications.
36 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics program and erase operations notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 2.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 1.8 volts, 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 10 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most bytes/words program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum byte/word program time specified is exceeded. see write operation status section for additional information. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m0 2 10 3 1s n t l w v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l w t h a e m i t d l o h s s e r d d an i m0 60 6s n t t s a t s e t t i b e l g g o t r o f e m i t p u t e s s s e r d d an i m5 1s n t t h a t s e t t i b e l g g o t r o f e m i t d l o h s s e r d d an i m0 s n t h w v d t s d e m i t p u t e s a t a dn i m0 60 6s n t x d h w t h d e m i t d l o h a t a dn i m0 s n t l w h g t l w h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0 s n t l w l e t s c e m i t p u t e s # e cn i m0 s n t h e h w t h c e m i t d l o h # e cn i m0 s n t h p e o t s e t t i b e l g g o t r o f e m i t h g i h e l b a n e t u p t u on i m0 2s n t h p e c t s e t t i b e l g g o t r o f e m i t h g i h e l b a n e p i h cn i m0 2s n t h w l w t p w h t d i w e s l u p e t i r wn i m0 50 5s n t l w h w t h p w h g i h h t d i w e s l u p e t i r wn i m0 3s n t w / r s s n o i t a r e p o e t i r w d n a d a e r n e e w t e b y c n e t a ln i m0 s n t 1 h w h w t 1 h w h w n o i t a r e p o g n i m m a r g o r p 3 , 2 , 1 e d o m e t y b p y t3 1s x a m0 0 3s e d o m d r o w p y t7 1s x a m0 6 3s g n i m m a r g o r p d e t a r e l e c c a n o i t a r e p o 3 , 2 , 1 v = c c a / # p w ( h h ) r o e t y b e d o m d r o w p y t3 1s x a m0 4 2s n o i t a r e p o g n i m m a r g o r p p i h c 5 , 3 , 2 , 1 e d o m e t y b p y t6 2c e s x a m0 6 1c e s e d o m d r o w p y t7 1c e s x a m6 9c e s t 2 h w h w t 2 h w h w n o i t a r e p o e s a r e r o t c e s 4 , 2 , 1 p y t1 c e s x a m0 1c e s t 3 h w h w t 3 h w h w n o i t a r e p o e s a r e p i h c 4 , 2 , 1 p y t5 3c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e 1 p y t0 0 0 , 0 0 0 , 1s e l c y c n i m0 0 0 , 0 0 1s e l c y c t s c v v c c e m i t p u t e s 1 n i m0 5s t b r # y b / y r m o r f e m i t y r e v o c e rn i m0 s n t y s u b y a l e d # y b / y r o t h g i h # e wn i m0 0 1s n
37 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. commands shown are for word mode operation. 3. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 19. program operation timings addresses ce# t wc 0x555 pa pa pa oe# t as t ah t wph t wp t ghwl t cs we# data t ds t dh 0xa0 pd status t whwh1 ry/by# t busy t rb t vcs v cc program command sequence (last two cycles) read status data (last two cycles) d out t ch
38 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics notes: 1. sa =sector address (for sector erase), va = valid address for reading status data (see write operation status section), d out is the true data at the read address. (0xff after an erase operation). 2. commands shown are for word mode operation. 3. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 20. sector/chip erase operation timings addresses ce# t wc 0x2aa va va sa oe# t as t ah t wph t wp t ghwl t cs t ch we# data t ds t dh 0x55 0x30 status d out t whwh2 or t whwh3 ry/by# t busy t rb t vcs v cc erase command sequence (last two cycles) read status data (last two cycles) address = 0x555 for chip erase data = 0x10 for chip erase
39 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics notes: 1. pa = program address, ra = read address, d out is the data at the read address. figure 21. back-to-back read/write operation timings t ce t acc t dh t wp t cph t wc valid d in valid d out valid d in data bus we# oe# ce# addresses valid pa valid ra valid pa valid pa valid d in t cp read cycle ce# controlled write cycles we# controlled write cycle t sr/w t rc t wc t wc t wph t ds t oeh t oe t oh t df t ghwl t as t ah
40 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics t busy t ch t oe t ce t rc complement complement true valid data status data status data data valid data ry/by# dq[6:0] dq[7] we# oe# ce# addresses va va va t acc t oeh t oh t df notes: 1. va = valid address for reading data# polling status data (see write operation status section). 2. illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. figure 22. data# polling timings (during automatic algorithms) notes: 1. va = valid address for reading toggle bits (dq[2], dq[6]) status data (see write operation status section). 2. illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle. figure 23. toggle polling timings (during automatic algorithms) t oeph t ast t busy t ch t oe t ce t rc valid status valid status valid status ry/by# dq[6], [2] we# oe# ce# addresses va va va t acc t oeh t oh t df va (second read) (first read) (stops toggling) valid data t aht t ceph
41 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics notes: 1. the system may use ce# or oe# to toggle dq[2] and dq[6]. dq[2] toggles only when read at an address within an erase-suspended sector. figure 24. dq[2] and dq[6] operation r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t r d i v v d i t c e t o r p n u r o t c e s y r a r o p m e t r o f e m i t n o i t i s n a r t 1 n i m0 0 5s n t h h v v h h g n i m m a r g o r p d e t a r e l e c c a r o f e m i t n o i t i s n a r t 1 n i m0 0 5s n t p s r r o f e m i t p u t e s # t e s e r t c e t o r p n u r o t c e s y r a r o p m e t n i m4 s t b r r t c e t o r p n u r o t c e s y r a r o p m e t r o f e m i t d l o h # t e s e rn i m4 s t t s r v d n a t c e t o r p p u o r g r o t c e s r o f e m i t p u t e s # t e s e r t c e t o r p n u n i m1 s t t o r p e m i t t c e t o r p p u o r g r o t c e sx a m0 5 1s t r p n u e m i t t c e t o r p n u r o t c e sx a m5 1s m t w r e v e m i t t i a w y f i r e v t c e t o r p n u / t c e t o r pn i m1 s sector group protect/unprotect, temporary sector unprotect, accelerated program notes: 1. not 100% tested. figure 25. temporary sector unprotect timings erase complete we# dq[6] dq[2] enter automatic erase erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase suspend t vidr ry/by# we# ce# reset# v id v il or v ih t rsp t vidr v il or v ih t rrb
42 hy29ds162/hy29ds163 r1.3/apr 01 note: for sector group protect, a[6] = 0, a[1] = 1, a[0] = 0. for sector unprotect, a[6] = 1, a[1] = 1, a[0] = 0. figure 27. sector group protect and unprotect timings ac characteristics figure 26. accelerated programming timings wp#/acc v hh v il or v ih t vhh t vhh v il or v ih v id v ih reset# don't care valid * valid * valid * sa, a[6], a[1], a[0] 0x60 0x60 0x40 status data ce# we# oe# t vrst t prot sector protect/unprotect verify t unpr t verw
43 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics alternate ce# controlled erase/program operations r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 2 1 - 3 1 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m0 2 10 3 1s n t l e v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l e t h a e m i t d l o h s s e r d d an i m0 60 6s n t h e v d t s d e m i t p u t e s a t a dn i m0 60 6s n t x d h e t h d e m i t d l o h a t a dn i m0 s n t l e h g t l e h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0 s n t l e l w t s w e m i t p u t e s # e wn i m0 s n t h w h e t h w e m i t d l o h # e wn i m0 s n t h e l e t p c h t d i w e s l u p # e cn i m0 50 5s n t l e h e t h p c h g i h h t d i w e s l u p # e cn i m0 3s n t 1 h w h w t 1 h w h w n o i t a r e p o g n i m m a r g o r p 3 , 2 , 1 e d o m e t y b p y t3 1s x a m0 0 3s e d o m d r o w p y t7 1s x a m0 6 3s g n i m m a r g o r p d e t a r e l e c c a n o i t a r e p o 3 , 2 , 1 v = c c a / # p w ( h h ) r o e t y b e d o m d r o w p y t3 1s x a m0 4 2s n o i t a r e p o g n i m m a r g o r p p i h c 5 , 3 , 2 , 1 e d o m e t y b p y t6 2c e s x a m0 6 1c e s e d o m d r o w p y t7 1c e s x a m6 9c e s t 2 h w h w t 2 h w h w n o i t a r e p o e s a r e r o t c e s 4 , 2 , 1 p y t1 c e s x a m0 1c e s t 3 h w h w t 3 h w h w n o i t a r e p o e s a r e p i h c 4 , 2 , 1 p y t5 3c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e 1 p y t0 0 0 , 0 0 0 , 1s e l c y c n i m0 0 0 , 0 0 1s e l c y c t y s u b y a l e d # y b / y r o t # e cn i m0 0 1s n notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 2.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 1.8 volts, 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 10 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum byte program time specified is exceeded. see write operation status section for additional information.
44 hy29ds162/hy29ds163 r1.3/apr 01 ac characteristics 0x555 for program 0x2aa for erase pa for program sa for sector erase 0x555 for chip erase t ws t rh t wh ce# oe# addresses t wc va t as t ah we# data ry/by# t ds status d out t busy t whwh1 or t whwh2 or t whwh3 t dh 0xa0 for program 0x55 for erase pd for program 0x30 for sector erase 0x10 for chip erase reset# t cp t cph t ghel notes: 1. pa = program address, pd = program data, va = valid address for reading program or erase status (see write operation status section), d out = array data read at va. 2. illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. 3. word mode addressing shown. 4. reset# shown only to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 28. alternate ce# controlled write operation timings
45 hy29ds162/hy29ds163 r1.3/apr 01 latchup characteristics notes: 1. includes all pins except v cc . test conditions: v cc = 1.8 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions: t a = 25 o c, f = 1.0 mhz. n o i t p i r c s e d m u m i n i m m u m i x a m t i n u v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i t p e c x e s n i p l l a n o ) # t e s e r d n a # e o , ] 9 [ a g n i d u l c n i ( 0 . 1 -0 . 1 1v v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i l l a n o5 . 0 -v c c 5 . 0 +v v c c t n e r r u c0 0 1 -0 0 1a m l o b m y s r e t e m a r a p p u t e s t s e t p y t x a m t i n u c n i e c n a t i c a p a c t u p n iv n i 0 =65 . 7f p c t u o e c n a t i c a p a c t u p t u ov t u o 0 =5 . 82 1f p c 2 n i e c n a t i c a p a c n i p l o r t n o cv n i 0 =5 . 79 f p data retention r e t e m a r a p s n o i t i d n o c t s e t m u m i n i m t i n u e m i t n o i t n e t e r a t a d n r e t t a p m u m i n i m c o 0 5 10 1s r a e y c o 5 2 10 2s r a e y package drawings physical dimensions tsop48 - 48-pin thin small outline package (measurements in millimeters) 18.30 18.50 pin 1 id 11.90 12.10 0.25mm (0.0098") bsc 1.20 max 1 24 48 25 19.80 20.20 0.50 bsc 0.95 1.05 0.50 0.70 0 5 o o 0.10 0.21 0.08 0.20 0.05 0.15
46 hy29ds162/hy29ds163 r1.3/apr 01 package drawings physical dimensions fbga48 - 48-ball fine-pitch ball grid array, 8 x 9 mm (measurements in millimeters) note: unless otherwise specified, tolerance = 0.05 mm 1.10 max 0.20 min c c 0.08 0.76 typ c 0.10 seating plane a1 corner index area 9.00 0.10 8.00 0.10 a b c 0.10 c 0.10 c c 2.10 0.10 1.80 0.10 pin a1 index mark 4.00 bsc 5.60 bsc a b c d e f g h 6 5 4 3 2 1 0.40 bsc 0.80 typ 0.40 bsc 0.30 0.05 ? ? 0.15 m c a b ? 0.08 m c c c
47 hy29ds162/hy29ds163 r1.3/apr 01 ordering information hynix products are available in several speeds, packages and operating temperature ranges. the ordering part number is formed by combining a number of fields, as indicated below. refer to the ? valid combinations ? table, which lists the configurations that are planned to be supported in volume. please contact your local hynix representative or distributor to confirm current availability of specific configura- tions and to determine if additional configurations have been released. valid combinations d e e p s d n a e g a k c a p a g b f p o s t e r u t a r e p m e t s n 0 2 1 s n 0 3 1 s n 0 2 1 s n 0 3 1 l a i c r e m m o c2 1 - f3 1 - f2 1 - t3 1 - t l a i r t s u d n ii 2 1 - fi 3 1 - fi 2 1 - ti 3 1 - t notes: 1. the complete part number is formed by appending the suffix shown in the table to the device number. for example, the part number for a 130 ns, industrial temperature range 2mb/14mb bank-split device in the tsop package with the top boot block option is hy29ds162tt-13i . 2. please contact your local hynix representative or distributor for current product availability. x 6 1 s d 9 2 y h xx-xxx s n o i t c u r t s n i l a i c e p s e g n a r e r u t a r e p m e t = k n a l b = i ) c 0 7 + o t 0 ( l a i c r e m m o c ) c 5 8 + o t 0 4 - ( l a i r t s u d n i n o i t p o d e e p s = 2 1 = 3 1 s n 0 2 1 s n 0 3 1 e p y t e g a k c a p = t = f ) p o s t ( e g a k c a p e n i l t u o l l a m s n i h t n i p - 8 4 m m 9 x 8 , ) a g b f ( y a r r a d i r g l l a b h c t i p - e n i f l l a b - 8 4 n o i t a c o l k c o l b t o o b = t = b n o i t p o k c o l b t o o b p o t n o i t p o k c o l b t o o b m o t t o b r e b m u n e c i v e d = 2 6 1 s d 9 2 y h = 3 6 1 s d 9 2 y h y l n o - t l o v 8 . 1 s o m c ) 6 1 x m 1 / 8 x m 2 ( t i b a g e m 6 1 t i l p s k n a b b m 4 1 / b m 2 h t i w y r o m e m h s a l f e s a r e r o t c e s y l n o - t l o v 8 . 1 s o m c ) 6 1 x m 1 / 8 x m 2 ( t i b a g e m 6 1 t i l p s k n a b b m 2 1 / b m 4 h t i w y r o m e m h s a l f e s a r e r o t c e s
48 hy29ds162/hy29ds163 r1.3/apr 01 d r o c e r n o i s i v e r . v e r e t a d s l i a t e d 0 . 10 0 / 5. e u s s i l a n i g i r o 1 . 10 0 / 7. n o i s r e v s n 0 3 1 d e d d a . n o i s r e v s n 0 2 1 d e v o m e r 2 . 10 0 / 1 1 . s n o i t a c i f i c e p s g n i m m a r g o r p p i h c d n a d r o w , e t y b d e g n a h c . ) 6 e l b a t ( s n o i t a r e p o l a r e v e s r o f t n e m e r i u q e r s a s s e r d d a k n a b d e v o m e r . ) d o h t e m e g a t l o v h g i h ( n o i t a r e p o d i c i n o r t c e l e f o n o i t p i r c s e d d e t c e r r o c . n o i t c e s n o i t p i r c s e d e d o m i f c n i s d n a m m o c t e s e r d n a y r e u q i f c f o n o i t p i r c s e d d e t c e r r o c . s n o i t c e r r o c l a c i h p a r g o p y t r o n i m 3 . 11 0 / 4 . t a m r o f x i n y h o t e g n a h c . f p 0 3 o t 0 5 m o r f c e p s e c n a t i c a p a c d a o l e g n a h c . n o i s r e v s n 0 2 1 d e d d a . n o i s r e v s n 0 5 1 d e v o m e r . a 2 . 0 o t 5 6 0 . 0 m o r f s t n e r r u c y b d n a t s p e e d d n a p e e l s l a c i p y t d e g n a h c . n o i t c e s i f c n i n o i t p i r c s e d l a n o i t a r e p o d e g n a h c d n a d n a m m o c y r e u q i f c o t s s e r d d a k n a b d e d d a . n o i t c n u f t a h t o t s e c n e r e f e r l l a d n a x i d n e p p a t c e t o r p n u / t c e t o r p p u o r g r o t c e s e g a t l o v - h g i h d e v o m e r i d e d d a c c a . s c i t s i r e t c a r a h c c d o t s n o i t a c i f i c e p s important notice ? 2001 by hynix semiconductor america. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of hynix semiconductor inc. or hynix semiconductor america (collec- tively ? hynix ? ). the information in this document is subject to change without notice. hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. devices sold by hynix are covered by warranty and patent in- demnification provisions appearing in hynix terms and condi- tions of sale only. hynix makes no warranty, express, statu- tory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. hynix makes no war- ranty of merchantability or fitness for any purpose. hynix ? s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific writ- ten agreement pertaining to such intended use is executed between the customer and hynix prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. memory sales and marketing division flash memory business unit hynix semiconductor inc. hynix semiconductor america inc. 10 fl., hynix youngdong building 3101 north first street 89, daechi-dong san jose, ca 95134 kangnam-gu usa seoul, korea telephone: (408) 232-8800 telephone: +82-2-580-5000 fax: (408) 232-8805 fax: +82-2-3459-3990 http://www.us.hynix.com http://www.hynix.com

▲Up To Search▲

Price & Availability of HY29DS163TF-13I

	To Download HY29DS163TF-13I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .